Lines Matching +full:0 +full:x6040
45 { 249600000, 2000000000, 0 },
50 .l = 0x3e,
51 .alpha = 0x8000,
52 .post_div_mask = 0xff << 8,
53 .post_div_val = 0x31 << 8,
54 .test_ctl_val = 0x40000000,
58 .offset = 0x0,
102 .l = 0x23,
103 .alpha = 0x6aaa,
104 .post_div_mask = 0xf << 8,
105 .post_div_val = 0x1 << 8,
106 .test_ctl_val = 0x40000000,
110 .offset = 0x1000,
142 .l = 0x64,
143 .post_div_val = 0x3 << 8,
144 .post_div_mask = 0x3 << 8,
147 .main_output_mask = BIT(0),
148 .config_ctl_hi_val = 0x400003d6,
149 .config_ctl_val = 0x20000954,
153 .offset = 0x2000,
181 .offset = 0x2000,
197 .offset = 0x2000,
214 .l = 0x27,
215 .alpha = 0x9555,
216 .post_div_mask = 0xf << 8,
217 .post_div_val = 0x1 << 8,
218 .test_ctl_val = 0x40000000,
222 .offset = 0x3000,
253 .offset = 0x4000,
284 { P_BI_TCXO, 0 },
300 { P_BI_TCXO, 0 },
318 { P_BI_TCXO_MX, 0 },
328 { P_BI_TCXO, 0 },
346 { P_BI_TCXO, 0 },
356 { P_BI_TCXO, 0 },
366 { P_BI_TCXO, 0 },
376 { P_CHIP_SLEEP_CLK, 0 },
384 { P_BI_TCXO, 0 },
394 { P_BI_TCXO, 0 },
402 F(19200000, P_BI_TCXO, 1, 0, 0),
403 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
404 F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0),
405 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
406 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
407 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
412 .cmd_rcgr = 0x7010,
413 .mnd_width = 0,
426 F(19200000, P_BI_TCXO, 1, 0, 0),
427 F(150000000, P_CAMCC_PLL0_OUT_EVEN, 4, 0, 0),
428 F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0),
429 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
430 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
431 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
436 .cmd_rcgr = 0xc12c,
437 .mnd_width = 0,
450 F(19200000, P_BI_TCXO, 1, 0, 0),
451 F(37500000, P_CAMCC_PLL0_OUT_EVEN, 16, 0, 0),
456 .cmd_rcgr = 0xc0c4,
470 .cmd_rcgr = 0xc0e0,
484 F(19200000, P_BI_TCXO, 1, 0, 0),
485 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
486 F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0),
487 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
492 .cmd_rcgr = 0xa064,
493 .mnd_width = 0,
506 F(19200000, P_BI_TCXO, 1, 0, 0),
507 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
512 .cmd_rcgr = 0x6004,
513 .mnd_width = 0,
526 .cmd_rcgr = 0x6028,
527 .mnd_width = 0,
540 .cmd_rcgr = 0x604c,
541 .mnd_width = 0,
554 .cmd_rcgr = 0x6070,
555 .mnd_width = 0,
568 F(19200000, P_BI_TCXO, 1, 0, 0),
569 F(50000000, P_CAMCC_PLL0_OUT_EVEN, 12, 0, 0),
570 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
571 F(200000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0),
572 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0),
573 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
578 .cmd_rcgr = 0x703c,
579 .mnd_width = 0,
592 F(19200000, P_BI_TCXO, 1, 0, 0),
593 F(380000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
594 F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0),
595 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
596 F(480000000, P_CAMCC_PLL2_OUT_EARLY, 2, 0, 0),
597 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
602 .cmd_rcgr = 0xc09c,
603 .mnd_width = 0,
617 F(19200000, P_BI_TCXO, 1, 0, 0),
618 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
619 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
624 .cmd_rcgr = 0xc074,
625 .mnd_width = 0,
638 F(19200000, P_BI_TCXO, 1, 0, 0),
639 F(380000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
640 F(510000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
641 F(637000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
642 F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
647 .cmd_rcgr = 0xa010,
648 .mnd_width = 0,
662 F(19200000, P_BI_TCXO, 1, 0, 0),
663 F(75000000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0),
664 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
665 F(384000000, P_CAMCC_PLL2_OUT_EARLY, 2.5, 0, 0),
666 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
671 .cmd_rcgr = 0xa03c,
672 .mnd_width = 0,
685 F(19200000, P_BI_TCXO, 1, 0, 0),
686 F(380000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
687 F(510000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
688 F(637000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
689 F(760000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
694 .cmd_rcgr = 0xb010,
695 .mnd_width = 0,
709 .cmd_rcgr = 0xb034,
710 .mnd_width = 0,
723 F(19200000, P_BI_TCXO, 1, 0, 0),
724 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
725 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
726 F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0),
727 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
732 .cmd_rcgr = 0xc004,
733 .mnd_width = 0,
746 .cmd_rcgr = 0xc020,
747 .mnd_width = 0,
760 F(19200000, P_BI_TCXO, 1, 0, 0),
761 F(340000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
762 F(430000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
763 F(520000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
764 F(600000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
769 .cmd_rcgr = 0x8010,
770 .mnd_width = 0,
784 .cmd_rcgr = 0xc048,
785 .mnd_width = 0,
798 F(19200000, P_BI_TCXO, 1, 0, 0),
799 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
800 F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0),
801 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
802 F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0),
803 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
808 .cmd_rcgr = 0xc100,
809 .mnd_width = 0,
822 F(19200000, P_BI_TCXO_MX, 1, 0, 0),
824 F(34285714, P_CAMCC_PLL2_OUT_AUX, 14, 0, 0),
829 .cmd_rcgr = 0x5004,
843 .cmd_rcgr = 0x5024,
857 .cmd_rcgr = 0x5044,
871 .cmd_rcgr = 0x5064,
885 F(32000, P_CHIP_SLEEP_CLK, 1, 0, 0),
890 .cmd_rcgr = 0xc1a4,
891 .mnd_width = 0,
904 F(19200000, P_BI_TCXO, 1, 0, 0),
905 F(80000000, P_CAMCC_PLL0_OUT_ODD, 5, 0, 0),
910 .cmd_rcgr = 0x7058,
911 .mnd_width = 0,
924 F(19200000, P_BI_TCXO, 1, 0, 0),
929 .cmd_rcgr = 0xc188,
930 .mnd_width = 0,
943 .halt_reg = 0x7070,
946 .enable_reg = 0x7070,
947 .enable_mask = BIT(0),
961 .halt_reg = 0x7054,
964 .enable_reg = 0x7054,
965 .enable_mask = BIT(0),
979 .halt_reg = 0x7038,
982 .enable_reg = 0x7038,
983 .enable_mask = BIT(0),
997 .halt_reg = 0x7028,
1000 .enable_reg = 0x7028,
1001 .enable_mask = BIT(0),
1015 .halt_reg = 0xc148,
1018 .enable_reg = 0xc148,
1019 .enable_mask = BIT(0),
1033 .halt_reg = 0xc150,
1036 .enable_reg = 0xc150,
1037 .enable_mask = BIT(0),
1051 .halt_reg = 0xc0dc,
1054 .enable_reg = 0xc0dc,
1055 .enable_mask = BIT(0),
1069 .halt_reg = 0xc0f8,
1072 .enable_reg = 0xc0f8,
1073 .enable_mask = BIT(0),
1087 .halt_reg = 0xc184,
1090 .enable_reg = 0xc184,
1091 .enable_mask = BIT(0),
1105 .halt_reg = 0xc124,
1108 .enable_reg = 0xc124,
1109 .enable_mask = BIT(0),
1123 .halt_reg = 0x601c,
1126 .enable_reg = 0x601c,
1127 .enable_mask = BIT(0),
1141 .halt_reg = 0x6040,
1144 .enable_reg = 0x6040,
1145 .enable_mask = BIT(0),
1159 .halt_reg = 0x6064,
1162 .enable_reg = 0x6064,
1163 .enable_mask = BIT(0),
1177 .halt_reg = 0x6088,
1180 .enable_reg = 0x6088,
1181 .enable_mask = BIT(0),
1195 .halt_reg = 0x6020,
1198 .enable_reg = 0x6020,
1199 .enable_mask = BIT(0),
1213 .halt_reg = 0x6044,
1216 .enable_reg = 0x6044,
1217 .enable_mask = BIT(0),
1231 .halt_reg = 0x6068,
1234 .enable_reg = 0x6068,
1235 .enable_mask = BIT(0),
1249 .halt_reg = 0x608c,
1252 .enable_reg = 0x608c,
1253 .enable_mask = BIT(0),
1267 .halt_reg = 0xc0b4,
1270 .enable_reg = 0xc0b4,
1271 .enable_mask = BIT(0),
1285 .halt_reg = 0xc0bc,
1288 .enable_reg = 0xc0bc,
1289 .enable_mask = BIT(0),
1303 .halt_reg = 0xc094,
1306 .enable_reg = 0xc094,
1307 .enable_mask = BIT(0),
1321 .halt_reg = 0xc08c,
1324 .enable_reg = 0xc08c,
1325 .enable_mask = BIT(0),
1339 .halt_reg = 0xa080,
1342 .enable_reg = 0xa080,
1343 .enable_mask = BIT(0),
1357 .halt_reg = 0xa028,
1360 .enable_reg = 0xa028,
1361 .enable_mask = BIT(0),
1375 .halt_reg = 0xa07c,
1378 .enable_reg = 0xa07c,
1379 .enable_mask = BIT(0),
1393 .halt_reg = 0xa054,
1396 .enable_reg = 0xa054,
1397 .enable_mask = BIT(0),
1411 .halt_reg = 0xa038,
1414 .enable_reg = 0xa038,
1415 .enable_mask = BIT(0),
1429 .halt_reg = 0xb058,
1432 .enable_reg = 0xb058,
1433 .enable_mask = BIT(0),
1447 .halt_reg = 0xb028,
1450 .enable_reg = 0xb028,
1451 .enable_mask = BIT(0),
1465 .halt_reg = 0xb054,
1468 .enable_reg = 0xb054,
1469 .enable_mask = BIT(0),
1483 .halt_reg = 0xb04c,
1486 .enable_reg = 0xb04c,
1487 .enable_mask = BIT(0),
1501 .halt_reg = 0xb030,
1504 .enable_reg = 0xb030,
1505 .enable_mask = BIT(0),
1519 .halt_reg = 0xc01c,
1522 .enable_reg = 0xc01c,
1523 .enable_mask = BIT(0),
1537 .halt_reg = 0xc040,
1540 .enable_reg = 0xc040,
1541 .enable_mask = BIT(0),
1555 .halt_reg = 0xc038,
1558 .enable_reg = 0xc038,
1559 .enable_mask = BIT(0),
1573 .halt_reg = 0x8040,
1576 .enable_reg = 0x8040,
1577 .enable_mask = BIT(0),
1591 .halt_reg = 0x803c,
1594 .enable_reg = 0x803c,
1595 .enable_mask = BIT(0),
1609 .halt_reg = 0x8038,
1612 .enable_reg = 0x8038,
1613 .enable_mask = BIT(0),
1627 .halt_reg = 0x8028,
1630 .enable_reg = 0x8028,
1631 .enable_mask = BIT(0),
1645 .halt_reg = 0x9028,
1648 .enable_reg = 0x9028,
1649 .enable_mask = BIT(0),
1663 .halt_reg = 0x9024,
1666 .enable_reg = 0x9024,
1667 .enable_mask = BIT(0),
1681 .halt_reg = 0x9020,
1684 .enable_reg = 0x9020,
1685 .enable_mask = BIT(0),
1699 .halt_reg = 0x9010,
1702 .enable_reg = 0x9010,
1703 .enable_mask = BIT(0),
1717 .halt_reg = 0xc060,
1720 .enable_reg = 0xc060,
1721 .enable_mask = BIT(0),
1735 .halt_reg = 0xc118,
1738 .enable_reg = 0xc118,
1739 .enable_mask = BIT(0),
1753 .halt_reg = 0x501c,
1756 .enable_reg = 0x501c,
1757 .enable_mask = BIT(0),
1771 .halt_reg = 0x503c,
1774 .enable_reg = 0x503c,
1775 .enable_mask = BIT(0),
1789 .halt_reg = 0x505c,
1792 .enable_reg = 0x505c,
1793 .enable_mask = BIT(0),
1807 .halt_reg = 0x507c,
1810 .enable_reg = 0x507c,
1811 .enable_mask = BIT(0),
1825 .halt_reg = 0xc1bc,
1828 .enable_reg = 0xc1bc,
1829 .enable_mask = BIT(0),
1845 .gdscr = 0x7004,
1854 .gdscr = 0xa004,
1864 .gdscr = 0xb004,
1874 .gdscr = 0x8004,
1883 .gdscr = 0x9004,
1892 .gdscr = 0xc1c4,
2010 .max_register = 0xd024,
2045 qcom_branch_set_clk_en(regmap, 0xc1a0); /* CAMCC_GDSC_CLK */ in camcc_sm7150_probe()