Lines Matching +full:0 +full:xf004
43 { 249600000, 2020000000, 0 },
47 { 864000000, 1056000000, 0 },
52 .l = 0x3e,
53 .alpha = 0x8000,
54 .config_ctl_val = 0x20485699,
55 .config_ctl_hi_val = 0x00182261,
56 .config_ctl_hi1_val = 0x32aa299c,
57 .user_ctl_val = 0x00008400,
58 .user_ctl_hi_val = 0x00000805,
62 .offset = 0x0,
79 { 0x1, 2 },
84 .offset = 0x0,
102 { 0x2, 3 },
107 .offset = 0x0,
126 .l = 0x1f,
127 .alpha = 0x4000,
128 .config_ctl_val = 0x20485699,
129 .config_ctl_hi_val = 0x00182261,
130 .config_ctl_hi1_val = 0x32aa299c,
131 .user_ctl_val = 0x00000400,
132 .user_ctl_hi_val = 0x00000805,
136 .offset = 0x1000,
153 { 0x1, 2 },
158 .offset = 0x1000,
177 .l = 0x32,
178 .alpha = 0x0,
179 .config_ctl_val = 0x90008820,
180 .config_ctl_hi_val = 0x00890263,
181 .config_ctl_hi1_val = 0x00000247,
182 .user_ctl_val = 0x00000400,
183 .user_ctl_hi_val = 0x00400000,
187 .offset = 0x2000,
204 { 0x1, 2 },
209 .offset = 0x2000,
228 .l = 0x1f,
229 .alpha = 0x4000,
230 .config_ctl_val = 0x20485699,
231 .config_ctl_hi_val = 0x00182261,
232 .config_ctl_hi1_val = 0x32aa299c,
233 .user_ctl_val = 0x00000400,
234 .user_ctl_hi_val = 0x00000805,
238 .offset = 0x3000,
255 { 0x1, 2 },
260 .offset = 0x3000,
279 .l = 0x24,
280 .alpha = 0x7555,
281 .config_ctl_val = 0x20485699,
282 .config_ctl_hi_val = 0x00182261,
283 .config_ctl_hi1_val = 0x32aa299c,
284 .user_ctl_val = 0x00000400,
285 .user_ctl_hi_val = 0x00000805,
289 .offset = 0x4000,
306 { 0x1, 2 },
311 .offset = 0x4000,
329 { P_BI_TCXO, 0 },
343 { P_BI_TCXO, 0 },
355 { P_BI_TCXO, 0 },
367 { P_BI_TCXO, 0 },
385 { P_BI_TCXO, 0 },
403 { P_BI_TCXO, 0 },
415 { P_BI_TCXO, 0 },
427 { P_BI_TCXO, 0 },
441 F(19200000, P_BI_TCXO, 1, 0, 0),
442 F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
443 F(410000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
444 F(460000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
445 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
446 F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
451 .cmd_rcgr = 0xa004,
452 .mnd_width = 0,
466 F(19200000, P_BI_TCXO, 1, 0, 0),
467 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
468 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0),
469 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
470 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
475 .cmd_rcgr = 0x13014,
476 .mnd_width = 0,
490 F(19200000, P_BI_TCXO, 1, 0, 0),
491 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
492 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
493 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
498 .cmd_rcgr = 0x10004,
513 .cmd_rcgr = 0x11004,
528 F(19200000, P_BI_TCXO, 1, 0, 0),
529 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
530 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
535 .cmd_rcgr = 0xc054,
536 .mnd_width = 0,
550 .cmd_rcgr = 0x16004,
551 .mnd_width = 0,
565 F(19200000, P_BI_TCXO, 1, 0, 0),
566 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
571 .cmd_rcgr = 0x9004,
572 .mnd_width = 0,
586 .cmd_rcgr = 0x9028,
587 .mnd_width = 0,
601 .cmd_rcgr = 0x904c,
602 .mnd_width = 0,
616 F(19200000, P_BI_TCXO, 1, 0, 0),
617 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
618 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
619 F(200000000, P_CAM_CC_PLL0_OUT_MAIN, 6, 0, 0),
620 F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0),
625 .cmd_rcgr = 0xa02c,
626 .mnd_width = 0,
640 F(19200000, P_BI_TCXO, 1, 0, 0),
641 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
642 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
643 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
648 .cmd_rcgr = 0xf014,
649 .mnd_width = 0,
665 F(64000000, P_CAM_CC_PLL2_OUT_MAIN, 15, 0, 0),
670 .cmd_rcgr = 0x8004,
685 .cmd_rcgr = 0x8024,
700 .cmd_rcgr = 0x8044,
715 .cmd_rcgr = 0x8064,
730 F(19200000, P_BI_TCXO, 1, 0, 0),
731 F(300000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
732 F(410000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
733 F(460000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
734 F(600000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
735 F(700000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
740 .cmd_rcgr = 0xb004,
741 .mnd_width = 0,
755 F(19200000, P_BI_TCXO, 1, 0, 0),
756 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
761 .cmd_rcgr = 0xa048,
762 .mnd_width = 0,
776 F(19200000, P_BI_TCXO, 1, 0, 0),
777 F(350000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
778 F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
779 F(548000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
780 F(630000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
785 .cmd_rcgr = 0xc004,
786 .mnd_width = 0,
800 .cmd_rcgr = 0xc02c,
801 .mnd_width = 0,
815 .cmd_rcgr = 0xd004,
816 .mnd_width = 0,
830 .cmd_rcgr = 0xd024,
831 .mnd_width = 0,
845 .halt_reg = 0xa060,
848 .enable_reg = 0xa060,
849 .enable_mask = BIT(0),
863 .halt_reg = 0xa044,
866 .enable_reg = 0xa044,
867 .enable_mask = BIT(0),
881 .halt_reg = 0xa01c,
884 .enable_reg = 0xa01c,
885 .enable_mask = BIT(0),
899 .halt_reg = 0x13034,
902 .enable_reg = 0x13034,
903 .enable_mask = BIT(0),
912 .halt_reg = 0x1302c,
915 .enable_reg = 0x1302c,
916 .enable_mask = BIT(0),
930 .halt_reg = 0x1300c,
933 .enable_reg = 0x1300c,
934 .enable_mask = BIT(0),
943 .halt_reg = 0x13004,
946 .enable_reg = 0x13004,
947 .enable_mask = BIT(0),
956 .halt_reg = 0x1001c,
959 .enable_reg = 0x1001c,
960 .enable_mask = BIT(0),
974 .halt_reg = 0x1101c,
977 .enable_reg = 0x1101c,
978 .enable_mask = BIT(0),
992 .halt_reg = 0x1401c,
995 .enable_reg = 0x1401c,
996 .enable_mask = BIT(0),
1010 .halt_reg = 0x12004,
1013 .enable_reg = 0x12004,
1014 .enable_mask = BIT(0),
1028 .halt_reg = 0x16020,
1031 .enable_reg = 0x16020,
1032 .enable_mask = BIT(0),
1046 .halt_reg = 0x1601c,
1049 .enable_reg = 0x1601c,
1050 .enable_mask = BIT(0),
1064 .halt_reg = 0x901c,
1067 .enable_reg = 0x901c,
1068 .enable_mask = BIT(0),
1082 .halt_reg = 0x9040,
1085 .enable_reg = 0x9040,
1086 .enable_mask = BIT(0),
1100 .halt_reg = 0x9064,
1103 .enable_reg = 0x9064,
1104 .enable_mask = BIT(0),
1118 .halt_reg = 0x9020,
1121 .enable_reg = 0x9020,
1122 .enable_mask = BIT(0),
1136 .halt_reg = 0x9044,
1139 .enable_reg = 0x9044,
1140 .enable_mask = BIT(0),
1154 .halt_reg = 0x9068,
1157 .enable_reg = 0x9068,
1158 .enable_mask = BIT(0),
1172 .halt_reg = 0xf004,
1175 .enable_reg = 0xf004,
1176 .enable_mask = BIT(0),
1185 .halt_reg = 0xf02c,
1188 .enable_reg = 0xf02c,
1189 .enable_mask = BIT(0),
1203 .halt_reg = 0xf008,
1206 .enable_reg = 0xf008,
1207 .enable_mask = BIT(0),
1216 .halt_reg = 0xf00c,
1219 .enable_reg = 0xf00c,
1220 .enable_mask = BIT(0),
1229 .halt_reg = 0x801c,
1232 .enable_reg = 0x801c,
1233 .enable_mask = BIT(0),
1247 .halt_reg = 0x803c,
1250 .enable_reg = 0x803c,
1251 .enable_mask = BIT(0),
1265 .halt_reg = 0x805c,
1268 .enable_reg = 0x805c,
1269 .enable_mask = BIT(0),
1283 .halt_reg = 0x807c,
1286 .enable_reg = 0x807c,
1287 .enable_mask = BIT(0),
1301 .halt_reg = 0xb030,
1304 .enable_reg = 0xb030,
1305 .enable_mask = BIT(0),
1319 .halt_reg = 0xb02c,
1322 .enable_reg = 0xb02c,
1323 .enable_mask = BIT(0),
1337 .halt_reg = 0xb01c,
1340 .enable_reg = 0xb01c,
1341 .enable_mask = BIT(0),
1355 .halt_reg = 0x14018,
1358 .enable_reg = 0x14018,
1359 .enable_mask = BIT(0),
1368 .halt_reg = 0xf034,
1371 .enable_reg = 0xf034,
1372 .enable_mask = BIT(0),
1381 .halt_reg = 0xc070,
1384 .enable_reg = 0xc070,
1385 .enable_mask = BIT(0),
1399 .halt_reg = 0xc01c,
1402 .enable_reg = 0xc01c,
1403 .enable_mask = BIT(0),
1417 .halt_reg = 0xc06c,
1420 .enable_reg = 0xc06c,
1421 .enable_mask = BIT(0),
1435 .halt_reg = 0xc044,
1438 .enable_reg = 0xc044,
1439 .enable_mask = BIT(0),
1453 .halt_reg = 0xd048,
1456 .enable_reg = 0xd048,
1457 .enable_mask = BIT(0),
1471 .halt_reg = 0xd01c,
1474 .enable_reg = 0xd01c,
1475 .enable_mask = BIT(0),
1489 .halt_reg = 0xd044,
1492 .enable_reg = 0xd044,
1493 .enable_mask = BIT(0),
1507 .halt_reg = 0xd03c,
1510 .enable_reg = 0xd03c,
1511 .enable_mask = BIT(0),
1525 .gdscr = 0x14004,
1526 .en_rest_wait_val = 0x2,
1527 .en_few_wait_val = 0x2,
1528 .clk_dis_wait_val = 0xf,
1616 [CAM_CC_BPS_BCR] = { 0xa000 },
1617 [CAM_CC_CAMNOC_BCR] = { 0x13000 },
1618 [CAM_CC_CAMSS_TOP_BCR] = { 0x14000 },
1619 [CAM_CC_CCI_0_BCR] = { 0x10000 },
1620 [CAM_CC_CCI_1_BCR] = { 0x11000 },
1621 [CAM_CC_CPAS_BCR] = { 0x12000 },
1622 [CAM_CC_CRE_BCR] = { 0x16000 },
1623 [CAM_CC_CSI0PHY_BCR] = { 0x9000 },
1624 [CAM_CC_CSI1PHY_BCR] = { 0x9024 },
1625 [CAM_CC_CSI2PHY_BCR] = { 0x9048 },
1626 [CAM_CC_ICP_BCR] = { 0xf000 },
1627 [CAM_CC_MCLK0_BCR] = { 0x8000 },
1628 [CAM_CC_MCLK1_BCR] = { 0x8020 },
1629 [CAM_CC_MCLK2_BCR] = { 0x8040 },
1630 [CAM_CC_MCLK3_BCR] = { 0x8060 },
1631 [CAM_CC_OPE_0_BCR] = { 0xb000 },
1632 [CAM_CC_TFE_0_BCR] = { 0xc000 },
1633 [CAM_CC_TFE_1_BCR] = { 0xd000 },
1640 .max_register = 0x16024,