Lines Matching +full:0 +full:x6040
49 { 249600000, 1800000000, 0 },
53 { 595200000, 3600000000, 0 },
57 .l = 0x3e,
58 .alpha = 0x8000,
59 .config_ctl_val = 0x20485699,
60 .config_ctl_hi_val = 0x00002261,
61 .config_ctl_hi1_val = 0x2a9a699c,
62 .test_ctl_val = 0x00000000,
63 .test_ctl_hi_val = 0x00000000,
64 .test_ctl_hi1_val = 0x01800000,
65 .user_ctl_val = 0x00003100,
66 .user_ctl_hi_val = 0x00000805,
67 .user_ctl_hi1_val = 0x00000000,
71 .offset = 0x0,
88 { 0x1, 2 },
92 .offset = 0x0,
110 { 0x3, 3 },
114 .offset = 0x0,
132 .l = 0x21,
133 .alpha = 0x5555,
134 .config_ctl_val = 0x20485699,
135 .config_ctl_hi_val = 0x00002261,
136 .config_ctl_hi1_val = 0x2a9a699c,
137 .test_ctl_val = 0x00000000,
138 .test_ctl_hi_val = 0x00000000,
139 .test_ctl_hi1_val = 0x01800000,
140 .user_ctl_val = 0x00000100,
141 .user_ctl_hi_val = 0x00000805,
142 .user_ctl_hi1_val = 0x00000000,
146 .offset = 0x1000,
163 { 0x1, 2 },
167 .offset = 0x1000,
185 .l = 0x32,
186 .alpha = 0x0,
187 .config_ctl_val = 0x08200800,
188 .config_ctl_hi_val = 0x05028011,
189 .config_ctl_hi1_val = 0x08000000,
193 .offset = 0x2000,
210 .l = 0x29,
211 .alpha = 0xaaaa,
212 .config_ctl_val = 0x20485699,
213 .config_ctl_hi_val = 0x00002261,
214 .config_ctl_hi1_val = 0x2a9a699c,
215 .test_ctl_val = 0x00000000,
216 .test_ctl_hi_val = 0x00000000,
217 .test_ctl_hi1_val = 0x01800000,
218 .user_ctl_val = 0x00000100,
219 .user_ctl_hi_val = 0x00000805,
220 .user_ctl_hi1_val = 0x00000000,
224 .offset = 0x3000,
241 { 0x1, 2 },
245 .offset = 0x3000,
263 .l = 0x29,
264 .alpha = 0xaaaa,
265 .config_ctl_val = 0x20485699,
266 .config_ctl_hi_val = 0x00002261,
267 .config_ctl_hi1_val = 0x2a9a699c,
268 .test_ctl_val = 0x00000000,
269 .test_ctl_hi_val = 0x00000000,
270 .test_ctl_hi1_val = 0x01800000,
271 .user_ctl_val = 0x00000100,
272 .user_ctl_hi_val = 0x00000805,
273 .user_ctl_hi1_val = 0x00000000,
277 .offset = 0x4000,
294 { 0x1, 2 },
298 .offset = 0x4000,
316 .l = 0x29,
317 .alpha = 0xaaaa,
318 .config_ctl_val = 0x20485699,
319 .config_ctl_hi_val = 0x00002261,
320 .config_ctl_hi1_val = 0x2a9a699c,
321 .test_ctl_val = 0x00000000,
322 .test_ctl_hi_val = 0x00000000,
323 .test_ctl_hi1_val = 0x01800000,
324 .user_ctl_val = 0x00000100,
325 .user_ctl_hi_val = 0x00000805,
326 .user_ctl_hi1_val = 0x00000000,
330 .offset = 0x10000,
347 { 0x1, 2 },
351 .offset = 0x10000,
369 .l = 0x29,
370 .alpha = 0xaaaa,
371 .config_ctl_val = 0x20486699,
372 .config_ctl_hi_val = 0x00002261,
373 .config_ctl_hi1_val = 0x2a9a699c,
374 .test_ctl_val = 0x00000000,
375 .test_ctl_hi_val = 0x00000000,
376 .test_ctl_hi1_val = 0x01800000,
377 .user_ctl_val = 0x00000100,
378 .user_ctl_hi_val = 0x00000805,
379 .user_ctl_hi1_val = 0x00000000,
383 .offset = 0x11000,
400 { 0x1, 2 },
404 .offset = 0x11000,
422 .l = 0x32,
423 .alpha = 0x0,
424 .config_ctl_val = 0x20485699,
425 .config_ctl_hi_val = 0x00002261,
426 .config_ctl_hi1_val = 0x2a9a699c,
427 .test_ctl_val = 0x00000000,
428 .test_ctl_hi_val = 0x00000000,
429 .test_ctl_hi1_val = 0x01800000,
430 .user_ctl_val = 0x00003100,
431 .user_ctl_hi_val = 0x00000805,
432 .user_ctl_hi1_val = 0x00000000,
436 .offset = 0x12000,
453 { 0x1, 2 },
457 .offset = 0x12000,
475 { 0x3, 3 },
479 .offset = 0x12000,
497 { P_BI_TCXO, 0 },
513 { P_BI_TCXO, 0 },
525 { P_BI_TCXO, 0 },
543 { P_BI_TCXO, 0 },
561 { P_BI_TCXO, 0 },
571 { P_BI_TCXO, 0 },
581 { P_BI_TCXO, 0 },
591 { P_BI_TCXO, 0 },
601 { P_BI_TCXO, 0 },
611 { P_SLEEP_CLK, 0 },
619 { P_BI_TCXO, 0 },
627 F(19200000, P_BI_TCXO, 1, 0, 0),
628 F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0),
629 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
630 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
631 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
632 F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
637 .cmd_rcgr = 0x7010,
638 .mnd_width = 0,
652 F(19200000, P_BI_TCXO, 1, 0, 0),
653 F(150000000, P_CAMCC_PLL0_OUT_EVEN, 4, 0, 0),
654 F(266666667, P_CAMCC_PLL0_OUT_ODD, 1.5, 0, 0),
655 F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0),
656 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
657 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
662 .cmd_rcgr = 0xc170,
663 .mnd_width = 0,
676 F(19200000, P_BI_TCXO, 1, 0, 0),
677 F(37500000, P_CAMCC_PLL0_OUT_EVEN, 16, 0, 0),
682 .cmd_rcgr = 0xc108,
696 .cmd_rcgr = 0xc124,
710 .cmd_rcgr = 0xc204,
724 .cmd_rcgr = 0xc220,
738 F(19200000, P_BI_TCXO, 1, 0, 0),
739 F(240000000, P_CAMCC_PLL0_OUT_EVEN, 2.5, 0, 0),
740 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
745 .cmd_rcgr = 0xa064,
746 .mnd_width = 0,
759 F(19200000, P_BI_TCXO, 1, 0, 0),
760 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
765 .cmd_rcgr = 0x6004,
766 .mnd_width = 0,
779 .cmd_rcgr = 0x6028,
780 .mnd_width = 0,
793 .cmd_rcgr = 0x604c,
794 .mnd_width = 0,
807 .cmd_rcgr = 0x6074,
808 .mnd_width = 0,
821 F(19200000, P_BI_TCXO, 1, 0, 0),
822 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
823 F(200000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0),
824 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0),
825 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
830 .cmd_rcgr = 0x703c,
831 .mnd_width = 0,
844 F(19200000, P_BI_TCXO, 1, 0, 0),
845 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
846 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
851 .cmd_rcgr = 0xc0b8,
852 .mnd_width = 0,
865 F(19200000, P_BI_TCXO, 1, 0, 0),
866 F(400000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
867 F(558000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
868 F(637000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
869 F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
874 .cmd_rcgr = 0xa010,
875 .mnd_width = 0,
889 F(19200000, P_BI_TCXO, 1, 0, 0),
890 F(75000000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0),
891 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
892 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
893 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
898 .cmd_rcgr = 0xa03c,
899 .mnd_width = 0,
912 F(19200000, P_BI_TCXO, 1, 0, 0),
913 F(400000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
914 F(558000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
915 F(637000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
916 F(760000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
921 .cmd_rcgr = 0xb010,
922 .mnd_width = 0,
936 .cmd_rcgr = 0xb03c,
937 .mnd_width = 0,
950 F(400000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),
951 F(558000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),
952 F(637000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),
953 F(760000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),
958 .cmd_rcgr = 0xf010,
959 .mnd_width = 0,
973 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
974 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
975 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
980 .cmd_rcgr = 0xf03c,
981 .mnd_width = 0,
994 F(19200000, P_BI_TCXO, 1, 0, 0),
995 F(400000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),
996 F(558000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),
997 F(637000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),
998 F(760000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),
1003 .cmd_rcgr = 0xf07c,
1004 .mnd_width = 0,
1018 .cmd_rcgr = 0xf0a8,
1019 .mnd_width = 0,
1032 F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0),
1033 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
1034 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
1035 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
1040 .cmd_rcgr = 0xc004,
1041 .mnd_width = 0,
1054 .cmd_rcgr = 0xc020,
1055 .mnd_width = 0,
1068 .cmd_rcgr = 0xc048,
1069 .mnd_width = 0,
1082 .cmd_rcgr = 0xc064,
1083 .mnd_width = 0,
1096 .cmd_rcgr = 0xc240,
1097 .mnd_width = 0,
1110 .cmd_rcgr = 0xc25c,
1111 .mnd_width = 0,
1124 .cmd_rcgr = 0xc284,
1125 .mnd_width = 0,
1138 .cmd_rcgr = 0xc2a0,
1139 .mnd_width = 0,
1152 F(19200000, P_BI_TCXO, 1, 0, 0),
1153 F(320000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
1154 F(475000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
1155 F(520000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
1156 F(600000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
1161 .cmd_rcgr = 0x8010,
1162 .mnd_width = 0,
1176 F(19200000, P_BI_TCXO, 1, 0, 0),
1177 F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0),
1178 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
1179 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
1180 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
1185 .cmd_rcgr = 0xc08c,
1186 .mnd_width = 0,
1199 F(240000000, P_CAMCC_PLL7_OUT_EVEN, 2, 0, 0),
1200 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
1201 F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0),
1202 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
1207 .cmd_rcgr = 0xc144,
1208 .mnd_width = 0,
1221 F(19200000, P_BI_TCXO, 1, 0, 0),
1223 F(64000000, P_CAMCC_PLL2_OUT_EARLY, 15, 0, 0),
1228 .cmd_rcgr = 0x5004,
1242 .cmd_rcgr = 0x5024,
1256 .cmd_rcgr = 0x5044,
1270 .cmd_rcgr = 0x5064,
1284 .cmd_rcgr = 0x5084,
1298 .cmd_rcgr = 0x50a4,
1312 .cmd_rcgr = 0x50c4,
1326 .cmd_rcgr = 0x50e4,
1340 F(32000, P_SLEEP_CLK, 1, 0, 0),
1345 .cmd_rcgr = 0xc1e8,
1346 .mnd_width = 0,
1359 F(19200000, P_BI_TCXO, 1, 0, 0),
1360 F(80000000, P_CAMCC_PLL7_OUT_EVEN, 6, 0, 0),
1365 .cmd_rcgr = 0x7058,
1379 F(19200000, P_BI_TCXO, 1, 0, 0),
1384 .cmd_rcgr = 0xc1cc,
1385 .mnd_width = 0,
1398 .halt_reg = 0x7070,
1401 .enable_reg = 0x7070,
1402 .enable_mask = BIT(0),
1416 .halt_reg = 0x7054,
1419 .enable_reg = 0x7054,
1420 .enable_mask = BIT(0),
1434 .halt_reg = 0x7038,
1437 .enable_reg = 0x7038,
1438 .enable_mask = BIT(0),
1452 .halt_reg = 0x7028,
1455 .enable_reg = 0x7028,
1456 .enable_mask = BIT(0),
1470 .halt_reg = 0xc18c,
1473 .enable_reg = 0xc18c,
1474 .enable_mask = BIT(0),
1488 .halt_reg = 0xc194,
1491 .enable_reg = 0xc194,
1492 .enable_mask = BIT(0),
1506 .halt_reg = 0xc120,
1509 .enable_reg = 0xc120,
1510 .enable_mask = BIT(0),
1524 .halt_reg = 0xc13c,
1527 .enable_reg = 0xc13c,
1528 .enable_mask = BIT(0),
1542 .halt_reg = 0xc21c,
1545 .enable_reg = 0xc21c,
1546 .enable_mask = BIT(0),
1560 .halt_reg = 0xc238,
1563 .enable_reg = 0xc238,
1564 .enable_mask = BIT(0),
1578 .halt_reg = 0xc1c8,
1581 .enable_reg = 0xc1c8,
1582 .enable_mask = BIT(0),
1596 .halt_reg = 0xc168,
1599 .enable_reg = 0xc168,
1600 .enable_mask = BIT(0),
1614 .halt_reg = 0x601c,
1617 .enable_reg = 0x601c,
1618 .enable_mask = BIT(0),
1632 .halt_reg = 0x6040,
1635 .enable_reg = 0x6040,
1636 .enable_mask = BIT(0),
1650 .halt_reg = 0x6064,
1653 .enable_reg = 0x6064,
1654 .enable_mask = BIT(0),
1668 .halt_reg = 0x608c,
1671 .enable_reg = 0x608c,
1672 .enable_mask = BIT(0),
1686 .halt_reg = 0x6020,
1689 .enable_reg = 0x6020,
1690 .enable_mask = BIT(0),
1704 .halt_reg = 0x6044,
1707 .enable_reg = 0x6044,
1708 .enable_mask = BIT(0),
1722 .halt_reg = 0x6068,
1725 .enable_reg = 0x6068,
1726 .enable_mask = BIT(0),
1740 .halt_reg = 0x6090,
1743 .enable_reg = 0x6090,
1744 .enable_mask = BIT(0),
1758 .halt_reg = 0xc1e4,
1761 .enable_reg = 0xc1e4,
1762 .enable_mask = BIT(0),
1776 .halt_reg = 0xc0d8,
1779 .enable_reg = 0xc0d8,
1780 .enable_mask = BIT(0),
1794 .halt_reg = 0xc0d0,
1797 .enable_reg = 0xc0d0,
1798 .enable_mask = BIT(0),
1812 .halt_reg = 0xa080,
1815 .enable_reg = 0xa080,
1816 .enable_mask = BIT(0),
1830 .halt_reg = 0xa028,
1833 .enable_reg = 0xa028,
1834 .enable_mask = BIT(0),
1848 .halt_reg = 0xa07c,
1851 .enable_reg = 0xa07c,
1852 .enable_mask = BIT(0),
1866 .halt_reg = 0xa054,
1869 .enable_reg = 0xa054,
1870 .enable_mask = BIT(0),
1884 .halt_reg = 0xa038,
1887 .enable_reg = 0xa038,
1888 .enable_mask = BIT(0),
1902 .halt_reg = 0xb068,
1905 .enable_reg = 0xb068,
1906 .enable_mask = BIT(0),
1920 .halt_reg = 0xb028,
1923 .enable_reg = 0xb028,
1924 .enable_mask = BIT(0),
1938 .halt_reg = 0xb064,
1941 .enable_reg = 0xb064,
1942 .enable_mask = BIT(0),
1956 .halt_reg = 0xb054,
1959 .enable_reg = 0xb054,
1960 .enable_mask = BIT(0),
1974 .halt_reg = 0xb038,
1977 .enable_reg = 0xb038,
1978 .enable_mask = BIT(0),
1992 .halt_reg = 0xf068,
1995 .enable_reg = 0xf068,
1996 .enable_mask = BIT(0),
2010 .halt_reg = 0xf028,
2013 .enable_reg = 0xf028,
2014 .enable_mask = BIT(0),
2028 .halt_reg = 0xf064,
2031 .enable_reg = 0xf064,
2032 .enable_mask = BIT(0),
2046 .halt_reg = 0xf054,
2049 .enable_reg = 0xf054,
2050 .enable_mask = BIT(0),
2064 .halt_reg = 0xf038,
2067 .enable_reg = 0xf038,
2068 .enable_mask = BIT(0),
2082 .halt_reg = 0xf0d4,
2085 .enable_reg = 0xf0d4,
2086 .enable_mask = BIT(0),
2100 .halt_reg = 0xf094,
2103 .enable_reg = 0xf094,
2104 .enable_mask = BIT(0),
2118 .halt_reg = 0xf0d0,
2121 .enable_reg = 0xf0d0,
2122 .enable_mask = BIT(0),
2136 .halt_reg = 0xf0c0,
2139 .enable_reg = 0xf0c0,
2140 .enable_mask = BIT(0),
2154 .halt_reg = 0xf0a4,
2157 .enable_reg = 0xf0a4,
2158 .enable_mask = BIT(0),
2172 .halt_reg = 0xc01c,
2175 .enable_reg = 0xc01c,
2176 .enable_mask = BIT(0),
2190 .halt_reg = 0xc040,
2193 .enable_reg = 0xc040,
2194 .enable_mask = BIT(0),
2208 .halt_reg = 0xc038,
2211 .enable_reg = 0xc038,
2212 .enable_mask = BIT(0),
2226 .halt_reg = 0xc060,
2229 .enable_reg = 0xc060,
2230 .enable_mask = BIT(0),
2244 .halt_reg = 0xc084,
2247 .enable_reg = 0xc084,
2248 .enable_mask = BIT(0),
2262 .halt_reg = 0xc07c,
2265 .enable_reg = 0xc07c,
2266 .enable_mask = BIT(0),
2280 .halt_reg = 0xc258,
2283 .enable_reg = 0xc258,
2284 .enable_mask = BIT(0),
2298 .halt_reg = 0xc27c,
2301 .enable_reg = 0xc27c,
2302 .enable_mask = BIT(0),
2316 .halt_reg = 0xc274,
2319 .enable_reg = 0xc274,
2320 .enable_mask = BIT(0),
2334 .halt_reg = 0xc29c,
2337 .enable_reg = 0xc29c,
2338 .enable_mask = BIT(0),
2352 .halt_reg = 0xc2c0,
2355 .enable_reg = 0xc2c0,
2356 .enable_mask = BIT(0),
2370 .halt_reg = 0xc2b8,
2373 .enable_reg = 0xc2b8,
2374 .enable_mask = BIT(0),
2388 .halt_reg = 0x8040,
2391 .enable_reg = 0x8040,
2392 .enable_mask = BIT(0),
2406 .halt_reg = 0x803c,
2409 .enable_reg = 0x803c,
2410 .enable_mask = BIT(0),
2424 .halt_reg = 0x8038,
2427 .enable_reg = 0x8038,
2428 .enable_mask = BIT(0),
2442 .halt_reg = 0x8028,
2445 .enable_reg = 0x8028,
2446 .enable_mask = BIT(0),
2460 .halt_reg = 0x9028,
2463 .enable_reg = 0x9028,
2464 .enable_mask = BIT(0),
2478 .halt_reg = 0x9024,
2481 .enable_reg = 0x9024,
2482 .enable_mask = BIT(0),
2496 .halt_reg = 0x9020,
2499 .enable_reg = 0x9020,
2500 .enable_mask = BIT(0),
2514 .halt_reg = 0x9010,
2517 .enable_reg = 0x9010,
2518 .enable_mask = BIT(0),
2532 .halt_reg = 0xc0a4,
2535 .enable_reg = 0xc0a4,
2536 .enable_mask = BIT(0),
2550 .halt_reg = 0xc15c,
2553 .enable_reg = 0xc15c,
2554 .enable_mask = BIT(0),
2568 .halt_reg = 0x501c,
2571 .enable_reg = 0x501c,
2572 .enable_mask = BIT(0),
2586 .halt_reg = 0x503c,
2589 .enable_reg = 0x503c,
2590 .enable_mask = BIT(0),
2604 .halt_reg = 0x505c,
2607 .enable_reg = 0x505c,
2608 .enable_mask = BIT(0),
2622 .halt_reg = 0x507c,
2625 .enable_reg = 0x507c,
2626 .enable_mask = BIT(0),
2640 .halt_reg = 0x509c,
2643 .enable_reg = 0x509c,
2644 .enable_mask = BIT(0),
2658 .halt_reg = 0x50bc,
2661 .enable_reg = 0x50bc,
2662 .enable_mask = BIT(0),
2676 .halt_reg = 0x50dc,
2679 .enable_reg = 0x50dc,
2680 .enable_mask = BIT(0),
2694 .halt_reg = 0x50fc,
2697 .enable_reg = 0x50fc,
2698 .enable_mask = BIT(0),
2712 .halt_reg = 0xc200,
2715 .enable_reg = 0xc200,
2716 .enable_mask = BIT(0),
2732 .gdscr = 0x7004,
2742 .gdscr = 0xa004,
2752 .gdscr = 0xb004,
2762 .gdscr = 0xf004,
2772 .gdscr = 0xf070,
2782 .gdscr = 0x8004,
2792 .gdscr = 0x9004,
2802 .gdscr = 0xc1bc,
2959 [CAMCC_BPS_BCR] = { 0x7000 },
2960 [CAMCC_CAMNOC_BCR] = { 0xc16c },
2961 [CAMCC_CCI_BCR] = { 0xc104 },
2962 [CAMCC_CPAS_BCR] = { 0xc164 },
2963 [CAMCC_CSI0PHY_BCR] = { 0x6000 },
2964 [CAMCC_CSI1PHY_BCR] = { 0x6024 },
2965 [CAMCC_CSI2PHY_BCR] = { 0x6048 },
2966 [CAMCC_CSI3PHY_BCR] = { 0x6070 },
2967 [CAMCC_ICP_BCR] = { 0xc0b4 },
2968 [CAMCC_IFE_0_BCR] = { 0xa000 },
2969 [CAMCC_IFE_1_BCR] = { 0xb000 },
2970 [CAMCC_IFE_2_BCR] = { 0xf000 },
2971 [CAMCC_IFE_3_BCR] = { 0xf06c },
2972 [CAMCC_IFE_LITE_0_BCR] = { 0xc000 },
2973 [CAMCC_IFE_LITE_1_BCR] = { 0xc044 },
2974 [CAMCC_IFE_LITE_2_BCR] = { 0xc23c },
2975 [CAMCC_IFE_LITE_3_BCR] = { 0xc280 },
2976 [CAMCC_IPE_0_BCR] = { 0x8000 },
2977 [CAMCC_IPE_1_BCR] = { 0x9000 },
2978 [CAMCC_JPEG_BCR] = { 0xc088 },
2979 [CAMCC_LRME_BCR] = { 0xc140 },
2986 .max_register = 0x13020,
3035 qcom_branch_set_clk_en(regmap, 0xc1e4); /* CAMCC_GDSC_CLK */ in camcc_sc8280xp_probe()
3043 return 0; in camcc_sc8280xp_probe()
3046 regmap_update_bits(regmap, 0xc1e4, BIT(0), 0); in camcc_sc8280xp_probe()