clk/qcom/apss-ipq-pll.c

12 	.offset = 0x0,
16 		.enable_reg = 0x0,
17 		.enable_mask = BIT(0),
30 	.offset = 0x0,
34 		.enable_reg = 0x0,
35 		.enable_mask = BIT(0),
48 	.offset = 0x0,
56 		.enable_reg = 0x0,
57 		.enable_mask = BIT(0),
71 	.l = 0x2a,
72 	.config_ctl_val = 0x4001075b,
73 	.main_output_mask = BIT(0),
77 	.status_val = 0x3,
80 	.test_ctl_hi_val = 0x00400003,
84 	.l = 0x2d,
85 	.config_ctl_val = 0x4001075b,
86 	.main_output_mask = BIT(0),
90 	.status_val = 0x3,
93 	.test_ctl_hi_val = 0x00400003,
97 	.l = 0x37,
98 	.config_ctl_val = 0x240d4828,
99 	.config_ctl_hi_val = 0x6,
103 	.main_output_mask = BIT(0),
104 	.test_ctl_val = 0x1c0000C0,
105 	.test_ctl_hi_val = 0x4000,
109 	.l = 0x48,
110 	.config_ctl_val = 0x200d4828,
111 	.config_ctl_hi_val = 0x6,
115 	.main_output_mask = BIT(0),
116 	.test_ctl_val = 0x1c000000,
117 	.test_ctl_hi_val = 0x4000,
121 	.l = 0x3b,
122 	.config_ctl_val = 0x200d4828,
123 	.config_ctl_hi_val = 0x6,
127 	.main_output_mask = BIT(0),
128 	.test_ctl_val = 0x0,
129 	.test_ctl_hi_val = 0x4000,
172 	.max_register		= 0x40,
184 	base = devm_platform_ioremap_resource(pdev, 0);  in apss_ipq_pll_probe()