1 // SPDX-License-Identifier: GPL-2.0-only
7  * Heavily inspired from former arch/arm/mach-pxa/pxa3xx.c
9  * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
14 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/pxa-clock.h>
22 #include "clk-pxa.h"
30 #define CKENA			(0x000C)	/* A Clock Enable Register */
31 #define CKENB			(0x0010)	/* B Clock Enable Register */
32 #define CKENC			(0x0024)	/* C Clock Enable Register */
38 #define ACCR_PCCE		(1 << 11)	/* Power Mode Change Clock Enable */
41 #define ACCR_SMCFS_MASK		(0x7 << 23)	/* Static Memory Controller Frequency Select */
44 #define ACCR_HSS_MASK		(0x3 << 14)	/* System Bus-Clock Frequency Select */
46 #define ACCR_XN_MASK		(0x7 << 8)	/* Core PLL Turbo-Mode-to-Run-Mode Ratio */
47 #define ACCR_XL_MASK		(0x1f)		/* Core PLL Run-Mode-to-Oscillator Ratio */
58  * Clock Enable Bit
60 #define CKEN_LCD	1	/* < LCD Clock Enable */
61 #define CKEN_USBH	2	/* < USB host clock enable */
62 #define CKEN_CAMERA	3	/* < Camera interface clock enable */
63 #define CKEN_NAND	4	/* < NAND Flash Controller Clock Enable */
64 #define CKEN_USB2	6	/* < USB 2.0 client clock enable. */
65 #define CKEN_DMC	8	/* < Dynamic Memory Controller clock enable */
66 #define CKEN_SMC	9	/* < Static Memory Controller clock enable */
67 #define CKEN_ISC	10	/* < Internal SRAM Controller clock enable */
68 #define CKEN_BOOT	11	/* < Boot rom clock enable */
69 #define CKEN_MMC1	12	/* < MMC1 Clock enable */
70 #define CKEN_MMC2	13	/* < MMC2 clock enable */
71 #define CKEN_KEYPAD	14	/* < Keypand Controller Clock Enable */
72 #define CKEN_CIR	15	/* < Consumer IR Clock Enable */
73 #define CKEN_USIM0	17	/* < USIM[0] Clock Enable */
74 #define CKEN_USIM1	18	/* < USIM[1] Clock Enable */
75 #define CKEN_TPM	19	/* < TPM clock enable */
76 #define CKEN_UDC	20	/* < UDC clock enable */
77 #define CKEN_BTUART	21	/* < BTUART clock enable */
78 #define CKEN_FFUART	22	/* < FFUART clock enable */
79 #define CKEN_STUART	23	/* < STUART clock enable */
80 #define CKEN_AC97	24	/* < AC97 clock enable */
81 #define CKEN_TOUCH	25	/* < Touch screen Interface Clock Enable */
82 #define CKEN_SSP1	26	/* < SSP1 clock enable */
83 #define CKEN_SSP2	27	/* < SSP2 clock enable */
84 #define CKEN_SSP3	28	/* < SSP3 clock enable */
85 #define CKEN_SSP4	29	/* < SSP4 clock enable */
86 #define CKEN_MSL0	30	/* < MSL0 clock enable */
87 #define CKEN_PWM0	32	/* < PWM[0] clock enable */
88 #define CKEN_PWM1	33	/* < PWM[1] clock enable */
89 #define CKEN_I2C	36	/* < I2C clock enable */
90 #define CKEN_INTC	38	/* < Interrupt controller clock enable */
91 #define CKEN_GPIO	39	/* < GPIO clock enable */
92 #define CKEN_1WIRE	40	/* < 1-wire clock enable */
93 #define CKEN_HSIO2	41	/* < HSIO2 clock enable */
94 #define CKEN_MINI_IM	48	/* < Mini-IM */
97 #define CKEN_MMC3	5	/* < MMC3 Clock Enable */
98 #define CKEN_MVED	43	/* < MVED clock enable */
100 /* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
101 #define CKEN_PXA300_GCU		42	/* Graphics controller clock enable */
102 #define CKEN_PXA320_GCU		7	/* Graphics controller clock enable */
117 static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
119 /* crystal frequency to static memory controller multiplier (SMCFS) */
120 static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
121 static const char * const get_freq_khz[] = {
125 static void __iomem *clk_regs;
160 void pxa3xx_clk_update_accr(u32 disable, u32 enable, u32 xclkcfg, u32 mask)  in pxa3xx_clk_update_accr()  argument
165 	accr |= enable;  in pxa3xx_clk_update_accr()
175 static unsigned long clk_pxa3xx_ac97_get_rate(struct clk_hw *hw,  in clk_pxa3xx_ac97_get_rate()
194 static unsigned long clk_pxa3xx_smemc_get_rate(struct clk_hw *hw,  in clk_pxa3xx_smemc_get_rate()
206 static bool pxa3xx_is_ring_osc_forced(void)  in pxa3xx_is_ring_osc_forced()
234 static struct desc_clk_cken pxa3xx_clocks[] __initdata = {
235 	PXA3XX_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 4, 1, 42, 1),
236 	PXA3XX_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 4, 1, 42, 1),
237 	PXA3XX_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 4, 1, 42, 1),
238 	PXA3XX_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 5, 1, 19, 0),
239 	PXA3XX_PBUS_CKEN("pxa27x-udc", NULL, UDC, 1, 4, 1, 13, 5),
240 	PXA3XX_PBUS_CKEN("pxa27x-ohci", NULL, USBH, 1, 4, 1, 13, 0),
241 	PXA3XX_PBUS_CKEN("pxa3xx-u2d", NULL, USB2, 1, 4, 1, 13, 0),
242 	PXA3XX_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 6, 1, 48, 0),
243 	PXA3XX_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 6, 1, 48, 0),
244 	PXA3XX_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC1, 1, 4, 1, 24, 0),
245 	PXA3XX_PBUS_CKEN("pxa2xx-mci.1", NULL, MMC2, 1, 4, 1, 24, 0),
246 	PXA3XX_PBUS_CKEN("pxa2xx-mci.2", NULL, MMC3, 1, 4, 1, 24, 0),
248 	PXA3XX_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD,
250 	PXA3XX_CKEN_1RATE("pxa3xx-ssp.0", NULL, SSP1, pxa3xx_13MHz_bus_parents),
251 	PXA3XX_CKEN_1RATE("pxa3xx-ssp.1", NULL, SSP2, pxa3xx_13MHz_bus_parents),
252 	PXA3XX_CKEN_1RATE("pxa3xx-ssp.2", NULL, SSP3, pxa3xx_13MHz_bus_parents),
253 	PXA3XX_CKEN_1RATE("pxa3xx-ssp.3", NULL, SSP4, pxa3xx_13MHz_bus_parents),
259 	PXA3XX_CKEN("pxa2xx-fb", NULL, pxa3xx_sbus_parents, 1, 1, 1, 1, LCD,
261 	PXA3XX_CKEN("pxa2xx-pcmcia", NULL, pxa3xx_smemcbus_parents, 1, 4,
265 static struct desc_clk_cken pxa300_310_clocks[] __initdata = {
267 	PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA300_GCU, 1, 1, 1, 1, 0),
268 	PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 4, 0),
269 	PXA3XX_CKEN_1RATE("pxa3xx-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
272 static struct desc_clk_cken pxa320_clocks[] __initdata = {
273 	PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 6, 0),
274 	PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA320_GCU, 1, 1, 1, 1, 0),
275 	PXA3XX_CKEN_1RATE("pxa3xx-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
278 static struct desc_clk_cken pxa93x_clocks[] __initdata = {
280 	PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA300_GCU, 1, 1, 1, 1, 0),
281 	PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 4, 0),
282 	PXA3XX_CKEN_1RATE("pxa93x-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
285 static unsigned long clk_pxa3xx_system_bus_get_rate(struct clk_hw *hw,  in clk_pxa3xx_system_bus_get_rate()
296 static u8 clk_pxa3xx_system_bus_get_parent(struct clk_hw *hw)  in clk_pxa3xx_system_bus_get_parent()
307 static unsigned long clk_pxa3xx_core_get_rate(struct clk_hw *hw,  in clk_pxa3xx_core_get_rate()
313 static u8 clk_pxa3xx_core_get_parent(struct clk_hw *hw)  in clk_pxa3xx_core_get_parent()
332 static unsigned long clk_pxa3xx_run_get_rate(struct clk_hw *hw,  in clk_pxa3xx_run_get_rate()
348 static unsigned long clk_pxa3xx_cpll_get_rate(struct clk_hw *hw,  in clk_pxa3xx_cpll_get_rate()
366 static void __init pxa3xx_register_core(void)  in pxa3xx_register_core()
375 static void __init pxa3xx_register_plls(void)  in pxa3xx_register_plls()
400 static struct dummy_clk dummy_clks[] __initdata = {
401 	DUMMY_CLK(NULL, "pxa93x-gpio", "osc_13mhz"),
402 	DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
403 	DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
404 	DUMMY_CLK(NULL, "pxa3xx-pwri2c.1", "osc_13mhz"),
407 static void __init pxa3xx_dummy_clocks_init(void)  in pxa3xx_dummy_clocks_init()
416 		name = d->dev_id ? d->dev_id : d->con_id;  in pxa3xx_dummy_clocks_init()
417 		clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);  in pxa3xx_dummy_clocks_init()
418 		clk_register_clkdev(clk, d->con_id, d->dev_id);  in pxa3xx_dummy_clocks_init()
422 static void __init pxa3xx_base_clocks_init(void __iomem *oscc_reg)  in pxa3xx_base_clocks_init()
435 			    clk_register_fixed_factor(NULL, "os-timer0",  in pxa3xx_base_clocks_init()
458 static void __init pxa3xx_dt_clocks_init(struct device_node *np)  in pxa3xx_dt_clocks_init()
463 CLK_OF_DECLARE(pxa_clks, "marvell,pxa300-clocks", pxa3xx_dt_clocks_init);