clk/pistachio/clk-pistachio.c

19 	GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
20 	GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),
21 	GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
22 	GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
23 	GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
24 	GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),
25 	GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
26 	GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
27 	GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),
28 	GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9),
29 	GATE(CLK_RPU_CORE, "rpu_core", "rpu_core_div", 0x104, 10),
30 	GATE(CLK_WIFI_ADC, "wifi_adc", "wifi_div8_mux", 0x104, 11),
31 	GATE(CLK_WIFI_DAC, "wifi_dac", "wifi_div4_mux", 0x104, 12),
32 	GATE(CLK_USB_PHY, "usb_phy", "usb_phy_div", 0x104, 13),
33 	GATE(CLK_ENET_IN, "enet_in", "enet_clk_in_gate", 0x104, 14),
34 	GATE(CLK_ENET, "enet", "enet_div", 0x104, 15),
35 	GATE(CLK_UART0, "uart0", "uart0_div", 0x104, 16),
36 	GATE(CLK_UART1, "uart1", "uart1_div", 0x104, 17),
37 	GATE(CLK_PERIPH_SYS, "periph_sys", "sys_internal_div", 0x104, 18),
38 	GATE(CLK_SPI0, "spi0", "spi0_div", 0x104, 19),
39 	GATE(CLK_SPI1, "spi1", "spi1_div", 0x104, 20),
40 	GATE(CLK_EVENT_TIMER, "event_timer", "event_timer_div", 0x104, 21),
42 	     0x104, 22),
43 	GATE(CLK_AUX_ADC, "aux_adc", "aux_adc_div", 0x104, 23),
44 	GATE(CLK_SD_HOST, "sd_host", "sd_host_div", 0x104, 24),
45 	GATE(CLK_BT, "bt", "bt_div", 0x104, 25),
46 	GATE(CLK_BT_DIV4, "bt_div4", "bt_div4_div", 0x104, 26),
47 	GATE(CLK_BT_DIV8, "bt_div8", "bt_div8_div", 0x104, 27),
48 	GATE(CLK_BT_1MHZ, "bt_1mhz", "bt_1mhz_div", 0x104, 28),
58 	    0x204, 2),
59 	DIV(CLK_MIPS_DIV, "mips_div", "mips_internal_div", 0x208, 8),
61 		0x20c, 8, CLK_DIVIDER_ROUND_CLOSEST),
63 		0x210, 8, CLK_DIVIDER_ROUND_CLOSEST),
65 		0x214, 8, CLK_DIVIDER_ROUND_CLOSEST),
67 		0x218, 8, CLK_DIVIDER_ROUND_CLOSEST),
68 	DIV(CLK_RPU_V_DIV, "rpu_v_div", "rpu_v_pll_mux", 0x21c, 2),
69 	DIV(CLK_RPU_L_DIV, "rpu_l_div", "rpu_l_mux", 0x220, 2),
70 	DIV(CLK_RPU_SLEEP_DIV, "rpu_sleep_div", "xtal", 0x224, 10),
71 	DIV(CLK_RPU_CORE_DIV, "rpu_core_div", "rpu_core_mux", 0x228, 3),
72 	DIV(CLK_USB_PHY_DIV, "usb_phy_div", "sys_internal_div", 0x22c, 6),
73 	DIV(CLK_ENET_DIV, "enet_div", "enet_mux", 0x230, 6),
75 	      0x234, 3, CLK_DIVIDER_ROUND_CLOSEST),
76 	DIV_F(CLK_UART0_DIV, "uart0_div", "uart0_internal_div", 0x238, 10,
79 	      0x23c, 3, CLK_DIVIDER_ROUND_CLOSEST),
80 	DIV_F(CLK_UART1_DIV, "uart1_div", "uart1_internal_div", 0x240, 10,
82 	DIV(CLK_SYS_INTERNAL_DIV, "sys_internal_div", "sys_pll_mux", 0x244, 3),
84 	    0x248, 3),
85 	DIV(CLK_SPI0_DIV, "spi0_div", "spi0_internal_div", 0x24c, 7),
87 	    0x250, 3),
88 	DIV(CLK_SPI1_DIV, "spi1_div", "spi1_internal_div", 0x254, 7),
90 	    "event_timer_mux", 0x258, 3),
92 	    0x25c, 12),
94 	    "aux_adc_internal", 0x260, 3),
95 	DIV(CLK_AUX_ADC_DIV, "aux_adc_div", "aux_adc_internal_div", 0x264, 10),
96 	DIV(CLK_SD_HOST_DIV, "sd_host_div", "sd_host_mux", 0x268, 6),
97 	DIV(CLK_BT_DIV, "bt_div", "bt_pll_mux", 0x26c, 6),
98 	DIV(CLK_BT_DIV4_DIV, "bt_div4_div", "bt_pll_mux", 0x270, 6),
99 	DIV(CLK_BT_DIV8_DIV, "bt_div8_div", "bt_pll_mux", 0x274, 6),
101 	    0x278, 3),
102 	DIV(CLK_BT_1MHZ_DIV, "bt_1mhz_div", "bt_1mhz_internal_div", 0x27c, 10),
125 	    0x200, 0),
126 	MUX(CLK_MIPS_PLL_MUX, "mips_pll_mux", mux_xtal_mips, 0x200, 1),
127 	MUX(CLK_AUDIO_PLL_MUX, "audio_pll_mux", mux_xtal_audio, 0x200, 2),
128 	MUX(CLK_AUDIO_MUX, "audio_mux", mux_audio_debug, 0x200, 4),
129 	MUX(CLK_RPU_V_PLL_MUX, "rpu_v_pll_mux", mux_xtal_rpu_v, 0x200, 5),
130 	MUX(CLK_RPU_L_PLL_MUX, "rpu_l_pll_mux", mux_xtal_rpu_l, 0x200, 6),
131 	MUX(CLK_RPU_L_MUX, "rpu_l_mux", mux_rpu_l_mips, 0x200, 7),
132 	MUX(CLK_WIFI_PLL_MUX, "wifi_pll_mux", mux_xtal_wifi, 0x200, 8),
133 	MUX(CLK_WIFI_DIV4_MUX, "wifi_div4_mux", mux_xtal_wifi_div4, 0x200, 9),
134 	MUX(CLK_WIFI_DIV8_MUX, "wifi_div8_mux", mux_xtal_wifi_div8, 0x200, 10),
135 	MUX(CLK_RPU_CORE_MUX, "rpu_core_mux", mux_wifi_div4_rpu_l, 0x200, 11),
136 	MUX(CLK_SYS_PLL_MUX, "sys_pll_mux", mux_xtal_sys, 0x200, 13),
137 	MUX(CLK_ENET_MUX, "enet_mux", mux_sys_enet, 0x200, 14),
138 	MUX(CLK_EVENT_TIMER_MUX, "event_timer_mux", mux_audio_sys, 0x200, 15),
139 	MUX(CLK_SD_HOST_MUX, "sd_host_mux", mux_sys_bt, 0x200, 16),
140 	MUX(CLK_BT_PLL_MUX, "bt_pll_mux", mux_xtal_bt, 0x200, 17),
144 	PLL_FIXED(CLK_MIPS_PLL, "mips_pll", "xtal", PLL_GF40LP_LAINT, 0x0),
146 		  PLL_GF40LP_FRAC, 0xc),
147 	PLL_FIXED(CLK_RPU_V_PLL, "rpu_v_pll", "xtal", PLL_GF40LP_LAINT, 0x20),
148 	PLL_FIXED(CLK_RPU_L_PLL, "rpu_l_pll", "xtal", PLL_GF40LP_LAINT, 0x2c),
149 	PLL_FIXED(CLK_SYS_PLL, "sys_pll", "xtal", PLL_GF40LP_FRAC, 0x38),
150 	PLL_FIXED(CLK_WIFI_PLL, "wifi_pll", "xtal", PLL_GF40LP_FRAC, 0x4c),
151 	PLL_FIXED(CLK_BT_PLL, "bt_pll", "xtal", PLL_GF40LP_LAINT, 0x60),
157 static const u32 mux_debug_idx[] = { 0x0, 0x1, 0x2, 0x4, 0x8, 0x10 };
193 					   p->base + 0x200, 18, 0x1f, 0,  in pistachio_clk_init()
205 	GATE(PERIPH_CLK_SYS, "sys", "periph_sys", 0x100, 0),
206 	GATE(PERIPH_CLK_SYS_BUS, "bus_sys", "periph_sys", 0x100, 1),
207 	GATE(PERIPH_CLK_DDR, "ddr", "periph_sys", 0x100, 2),
208 	GATE(PERIPH_CLK_ROM, "rom", "rom_div", 0x100, 3),
210 	     0x100, 4),
212 	     0x100, 5),
213 	GATE(PERIPH_CLK_IR, "ir", "ir_div", 0x100, 6),
214 	GATE(PERIPH_CLK_WD, "wd", "wd_div", 0x100, 7),
215 	GATE(PERIPH_CLK_PDM, "pdm", "pdm_div", 0x100, 8),
216 	GATE(PERIPH_CLK_PWM, "pwm", "pwm_div", 0x100, 9),
217 	GATE(PERIPH_CLK_I2C0, "i2c0", "i2c0_div", 0x100, 10),
218 	GATE(PERIPH_CLK_I2C1, "i2c1", "i2c1_div", 0x100, 11),
219 	GATE(PERIPH_CLK_I2C2, "i2c2", "i2c2_div", 0x100, 12),
220 	GATE(PERIPH_CLK_I2C3, "i2c3", "i2c3_div", 0x100, 13),
224 	DIV(PERIPH_CLK_ROM_DIV, "rom_div", "periph_sys", 0x10c, 7),
226 	    0x110, 7),
228 	    "periph_sys", 0x114, 7),
230 	    "counter_slow_pre_div", 0x118, 7),
231 	DIV_F(PERIPH_CLK_IR_PRE_DIV, "ir_pre_div", "periph_sys", 0x11c, 7,
233 	DIV_F(PERIPH_CLK_IR_DIV, "ir_div", "ir_pre_div", 0x120, 7,
235 	DIV_F(PERIPH_CLK_WD_PRE_DIV, "wd_pre_div", "periph_sys", 0x124, 7,
237 	DIV_F(PERIPH_CLK_WD_DIV, "wd_div", "wd_pre_div", 0x128, 7,
239 	DIV(PERIPH_CLK_PDM_PRE_DIV, "pdm_pre_div", "periph_sys", 0x12c, 7),
240 	DIV(PERIPH_CLK_PDM_DIV, "pdm_div", "pdm_pre_div", 0x130, 7),
241 	DIV(PERIPH_CLK_PWM_PRE_DIV, "pwm_pre_div", "periph_sys", 0x134, 7),
242 	DIV(PERIPH_CLK_PWM_DIV, "pwm_div", "pwm_pre_div", 0x138, 7),
243 	DIV(PERIPH_CLK_I2C0_PRE_DIV, "i2c0_pre_div", "periph_sys", 0x13c, 7),
244 	DIV(PERIPH_CLK_I2C0_DIV, "i2c0_div", "i2c0_pre_div", 0x140, 7),
245 	DIV(PERIPH_CLK_I2C1_PRE_DIV, "i2c1_pre_div", "periph_sys", 0x144, 7),
246 	DIV(PERIPH_CLK_I2C1_DIV, "i2c1_div", "i2c1_pre_div", 0x148, 7),
247 	DIV(PERIPH_CLK_I2C2_PRE_DIV, "i2c2_pre_div", "periph_sys", 0x14c, 7),
248 	DIV(PERIPH_CLK_I2C2_DIV, "i2c2_div", "i2c2_pre_div", 0x150, 7),
249 	DIV(PERIPH_CLK_I2C3_PRE_DIV, "i2c3_pre_div", "periph_sys", 0x154, 7),
250 	DIV(PERIPH_CLK_I2C3_DIV, "i2c3_div", "i2c3_pre_div", 0x158, 7),
275 	GATE(SYS_CLK_I2C0, "i2c0_sys", "sys", 0x8, 0),
276 	GATE(SYS_CLK_I2C1, "i2c1_sys", "sys", 0x8, 1),
277 	GATE(SYS_CLK_I2C2, "i2c2_sys", "sys", 0x8, 2),
278 	GATE(SYS_CLK_I2C3, "i2c3_sys", "sys", 0x8, 3),
279 	GATE(SYS_CLK_I2S_IN, "i2s_in_sys", "sys", 0x8, 4),
280 	GATE(SYS_CLK_PAUD_OUT, "paud_out_sys", "sys", 0x8, 5),
281 	GATE(SYS_CLK_SPDIF_OUT, "spdif_out_sys", "sys", 0x8, 6),
282 	GATE(SYS_CLK_SPI0_MASTER, "spi0_master_sys", "sys", 0x8, 7),
283 	GATE(SYS_CLK_SPI0_SLAVE, "spi0_slave_sys", "sys", 0x8, 8),
284 	GATE(SYS_CLK_PWM, "pwm_sys", "sys", 0x8, 9),
285 	GATE(SYS_CLK_UART0, "uart0_sys", "sys", 0x8, 10),
286 	GATE(SYS_CLK_UART1, "uart1_sys", "sys", 0x8, 11),
287 	GATE(SYS_CLK_SPI1, "spi1_sys", "sys", 0x8, 12),
288 	GATE(SYS_CLK_MDC, "mdc_sys", "sys", 0x8, 13),
289 	GATE(SYS_CLK_SD_HOST, "sd_host_sys", "sys", 0x8, 14),
290 	GATE(SYS_CLK_ENET, "enet_sys", "sys", 0x8, 15),
291 	GATE(SYS_CLK_IR, "ir_sys", "sys", 0x8, 16),
292 	GATE(SYS_CLK_WD, "wd_sys", "sys", 0x8, 17),
293 	GATE(SYS_CLK_TIMER, "timer_sys", "sys", 0x8, 18),
294 	GATE(SYS_CLK_I2S_OUT, "i2s_out_sys", "sys", 0x8, 24),
295 	GATE(SYS_CLK_SPDIF_IN, "spdif_in_sys", "sys", 0x8, 25),
296 	GATE(SYS_CLK_EVENT_TIMER, "event_timer_sys", "sys", 0x8, 26),
297 	GATE(SYS_CLK_HASH, "hash_sys", "sys", 0x8, 27),
317 	GATE(EXT_CLK_ENET_IN, "enet_clk_in_gate", "enet_clk_in", 0x58, 5),
318 	GATE(EXT_CLK_AUDIO_IN, "audio_clk_in_gate", "audio_clk_in", 0x58, 8)