99 static unsigned long ma35d1_calc_pll_freq(u8 mode, u32 *reg_ctl, unsigned long parent_rate)  in ma35d1_calc_pll_freq()  argument
104 	if (reg_ctl[1] & PLL_CTL1_BP)  in ma35d1_calc_pll_freq()
107 	n = FIELD_GET(PLL_CTL0_FBDIV, reg_ctl[0]);  in ma35d1_calc_pll_freq()
108 	m = FIELD_GET(PLL_CTL0_INDIV, reg_ctl[0]);  in ma35d1_calc_pll_freq()
109 	p = FIELD_GET(PLL_CTL1_OUTDIV, reg_ctl[1]);  in ma35d1_calc_pll_freq()
115 		x = FIELD_GET(PLL_CTL1_FRAC, reg_ctl[1]);  in ma35d1_calc_pll_freq()
124 				   unsigned long parent_rate, u32 *reg_ctl,  in ma35d1_pll_find_closest()  argument
169 					reg_ctl[0] = FIELD_PREP(PLL_CTL0_INDIV, m) |  in ma35d1_pll_find_closest()
171 					reg_ctl[1] = FIELD_PREP(PLL_CTL1_OUTDIV, p);  in ma35d1_pll_find_closest()
189 	u32 reg_ctl[3] = { 0 };  in ma35d1_clk_pll_set_rate()  local
196 	ret = ma35d1_pll_find_closest(pll, rate, parent_rate, reg_ctl, &pll_freq);  in ma35d1_clk_pll_set_rate()
202 		reg_ctl[0] |= FIELD_PREP(PLL_CTL0_MODE, PLL_MODE_INT);  in ma35d1_clk_pll_set_rate()
205 		reg_ctl[0] |= FIELD_PREP(PLL_CTL0_MODE, PLL_MODE_FRAC);  in ma35d1_clk_pll_set_rate()
208 		reg_ctl[0] |= FIELD_PREP(PLL_CTL0_MODE, PLL_MODE_SS) |  in ma35d1_clk_pll_set_rate()
210 		reg_ctl[2] = FIELD_PREP(PLL_CTL2_SLOPE, PLL_SLOPE);  in ma35d1_clk_pll_set_rate()
213 	reg_ctl[1] |= PLL_CTL1_PD;  in ma35d1_clk_pll_set_rate()
215 	writel_relaxed(reg_ctl[0], pll->ctl0_base);  in ma35d1_clk_pll_set_rate()
216 	writel_relaxed(reg_ctl[1], pll->ctl1_base);  in ma35d1_clk_pll_set_rate()
217 	writel_relaxed(reg_ctl[2], pll->ctl2_base);  in ma35d1_clk_pll_set_rate()
224 	u32 reg_ctl[3];  in ma35d1_clk_pll_recalc_rate()  local
232 		reg_ctl[0] = readl_relaxed(pll->ctl0_base);  in ma35d1_clk_pll_recalc_rate()
233 		pll_freq = ma35d1_calc_smic_pll_freq(reg_ctl[0], parent_rate);  in ma35d1_clk_pll_recalc_rate()
239 		reg_ctl[0] = readl_relaxed(pll->ctl0_base);  in ma35d1_clk_pll_recalc_rate()
240 		reg_ctl[1] = readl_relaxed(pll->ctl1_base);  in ma35d1_clk_pll_recalc_rate()
241 		pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, parent_rate);  in ma35d1_clk_pll_recalc_rate()
251 	u32 reg_ctl[3] = { 0 };  in ma35d1_clk_pll_round_rate()  local
258 	ret = ma35d1_pll_find_closest(pll, rate, *parent_rate, reg_ctl, &pll_freq);  in ma35d1_clk_pll_round_rate()
264 		reg_ctl[0] = readl_relaxed(pll->ctl0_base);  in ma35d1_clk_pll_round_rate()
265 		pll_freq = ma35d1_calc_smic_pll_freq(reg_ctl[0], *parent_rate);  in ma35d1_clk_pll_round_rate()
271 		reg_ctl[0] = readl_relaxed(pll->ctl0_base);  in ma35d1_clk_pll_round_rate()
272 		reg_ctl[1] = readl_relaxed(pll->ctl1_base);  in ma35d1_clk_pll_round_rate()
273 		pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, *parent_rate);  in ma35d1_clk_pll_round_rate()