1 // SPDX-License-Identifier: GPL-2.0-only
4  * Author: Chi-Fang Li <cfli0@nuvoton.com>
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
18 #include "clk-ma35d1.h"
20 /* PLL frequency limits */
36 /* bit fields for REG_CLK_PLL0CTL0, which is SMIC PLL design */
70 	u8 mode;  member
99 static unsigned long ma35d1_calc_pll_freq(u8 mode, u32 *reg_ctl, unsigned long parent_rate)  in ma35d1_calc_pll_freq()  argument
111 	if (mode == PLL_MODE_INT) {  in ma35d1_calc_pll_freq()
123 static int ma35d1_pll_find_closest(struct ma35d1_clk_pll *pll, unsigned long rate,  in ma35d1_pll_find_closest()  argument
133 		return -EINVAL;  in ma35d1_pll_find_closest()
135 	if (pll->mode == PLL_MODE_INT) {  in ma35d1_pll_find_closest()
155 				if (pll->mode != PLL_MODE_INT)  in ma35d1_pll_find_closest()
167 				diff = abs(rate - fout);  in ma35d1_pll_find_closest()
181 		return -EINVAL; /* cannot find even one valid setting */  in ma35d1_pll_find_closest()
188 	struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw);  in ma35d1_clk_pll_set_rate()  local
194 		return -EINVAL;  in ma35d1_clk_pll_set_rate()
196 	ret = ma35d1_pll_find_closest(pll, rate, parent_rate, reg_ctl, &pll_freq);  in ma35d1_clk_pll_set_rate()
200 	switch (pll->mode) {  in ma35d1_clk_pll_set_rate()
215 	writel_relaxed(reg_ctl[0], pll->ctl0_base);  in ma35d1_clk_pll_set_rate()
216 	writel_relaxed(reg_ctl[1], pll->ctl1_base);  in ma35d1_clk_pll_set_rate()
217 	writel_relaxed(reg_ctl[2], pll->ctl2_base);  in ma35d1_clk_pll_set_rate()
223 	struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw);  in ma35d1_clk_pll_recalc_rate()  local
230 	switch (pll->id) {  in ma35d1_clk_pll_recalc_rate()
232 		reg_ctl[0] = readl_relaxed(pll->ctl0_base);  in ma35d1_clk_pll_recalc_rate()
239 		reg_ctl[0] = readl_relaxed(pll->ctl0_base);  in ma35d1_clk_pll_recalc_rate()
240 		reg_ctl[1] = readl_relaxed(pll->ctl1_base);  in ma35d1_clk_pll_recalc_rate()
241 		pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, parent_rate);  in ma35d1_clk_pll_recalc_rate()
250 	struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw);  in ma35d1_clk_pll_round_rate()  local
256 		return -EINVAL;  in ma35d1_clk_pll_round_rate()
258 	ret = ma35d1_pll_find_closest(pll, rate, *parent_rate, reg_ctl, &pll_freq);  in ma35d1_clk_pll_round_rate()
262 	switch (pll->id) {  in ma35d1_clk_pll_round_rate()
264 		reg_ctl[0] = readl_relaxed(pll->ctl0_base);  in ma35d1_clk_pll_round_rate()
271 		reg_ctl[0] = readl_relaxed(pll->ctl0_base);  in ma35d1_clk_pll_round_rate()
272 		reg_ctl[1] = readl_relaxed(pll->ctl1_base);  in ma35d1_clk_pll_round_rate()
273 		pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, *parent_rate);  in ma35d1_clk_pll_round_rate()
281 	struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw);  in ma35d1_clk_pll_is_prepared()  local
282 	u32 val = readl_relaxed(pll->ctl1_base);  in ma35d1_clk_pll_is_prepared()
289 	struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw);  in ma35d1_clk_pll_prepare()  local
292 	val = readl_relaxed(pll->ctl1_base);  in ma35d1_clk_pll_prepare()
294 	writel_relaxed(val, pll->ctl1_base);  in ma35d1_clk_pll_prepare()
300 	struct ma35d1_clk_pll *pll = to_ma35d1_clk_pll(hw);  in ma35d1_clk_pll_unprepare()  local
303 	val = readl_relaxed(pll->ctl1_base);  in ma35d1_clk_pll_unprepare()
305 	writel_relaxed(val, pll->ctl1_base);  in ma35d1_clk_pll_unprepare()
327 	struct ma35d1_clk_pll *pll;  in ma35d1_reg_clk_pll()  local
331 	pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);  in ma35d1_reg_clk_pll()
332 	if (!pll)  in ma35d1_reg_clk_pll()
333 		return ERR_PTR(-ENOMEM);  in ma35d1_reg_clk_pll()
335 	pll->id = id;  in ma35d1_reg_clk_pll()
336 	pll->mode = u8mode;  in ma35d1_reg_clk_pll()
337 	pll->ctl0_base = base + REG_PLL_CTL0_OFFSET;  in ma35d1_reg_clk_pll()
338 	pll->ctl1_base = base + REG_PLL_CTL1_OFFSET;  in ma35d1_reg_clk_pll()
339 	pll->ctl2_base = base + REG_PLL_CTL2_OFFSET;  in ma35d1_reg_clk_pll()
352 	pll->hw.init = &init;  in ma35d1_reg_clk_pll()
353 	hw = &pll->hw;  in ma35d1_reg_clk_pll()