Lines Matching +full:ma35d1 +full:- +full:clk

1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chi-Fang Li <cfli0@nuvoton.com>
7 #include <linux/clk-provider.h>
12 #include "clk-ma35d1.h"
35 val = readl_relaxed(dclk->reg) >> dclk->shift; in ma35d1_clkdiv_recalc_rate()
36 val &= clk_div_mask(dclk->width); in ma35d1_clkdiv_recalc_rate()
38 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in ma35d1_clkdiv_recalc_rate()
39 CLK_DIVIDER_ROUND_CLOSEST, dclk->width); in ma35d1_clkdiv_recalc_rate()
46 return divider_round_rate(hw, rate, prate, dclk->table, in ma35d1_clkdiv_round_rate()
47 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in ma35d1_clkdiv_round_rate()
57 value = divider_get_val(rate, parent_rate, dclk->table, in ma35d1_clkdiv_set_rate()
58 dclk->width, CLK_DIVIDER_ROUND_CLOSEST); in ma35d1_clkdiv_set_rate()
60 spin_lock_irqsave(dclk->lock, flags); in ma35d1_clkdiv_set_rate()
62 data = readl_relaxed(dclk->reg); in ma35d1_clkdiv_set_rate()
63 data &= ~(clk_div_mask(dclk->width) << dclk->shift); in ma35d1_clkdiv_set_rate()
64 data |= (value - 1) << dclk->shift; in ma35d1_clkdiv_set_rate()
65 data |= dclk->mask; in ma35d1_clkdiv_set_rate()
66 writel_relaxed(data, dclk->reg); in ma35d1_clkdiv_set_rate()
68 spin_unlock_irqrestore(dclk->lock, flags); in ma35d1_clkdiv_set_rate()
94 return ERR_PTR(-ENOMEM); in ma35d1_reg_adc_clkdiv()
101 return ERR_PTR(-ENOMEM); in ma35d1_reg_adc_clkdiv()
118 div->reg = reg; in ma35d1_reg_adc_clkdiv()
119 div->shift = shift; in ma35d1_reg_adc_clkdiv()
120 div->width = width; in ma35d1_reg_adc_clkdiv()
121 div->mask = mask_bit ? BIT(mask_bit) : 0; in ma35d1_reg_adc_clkdiv()
122 div->lock = lock; in ma35d1_reg_adc_clkdiv()
123 div->hw.init = &init; in ma35d1_reg_adc_clkdiv()
124 div->table = table; in ma35d1_reg_adc_clkdiv()
126 hw = &div->hw; in ma35d1_reg_adc_clkdiv()