35 #define SAIF1			(CLKCTRL + 0x0110)  macro
59  *  DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
60  *		clock pins selected for SAIF1 input clocks.
61  *  CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
62  *		SAIF0 clock inputs selected for SAIF1 input clocks.
63  *  EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
65  *  EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
97 	val = readl_relaxed(SAIF1);  in clk_misc_init()
99 	writel_relaxed(val, SAIF1);  in clk_misc_init()
140 	ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm,  enumerator
205 	clks[saif1_div] = mxs_clk_frac("saif1_div", "saif1_sel", SAIF1, 0, 16, 29);  in mx28_clocks_init()
221 	clks[saif1] = mxs_clk_gate("saif1", "saif1_div", SAIF1, 31);  in mx28_clocks_init()