34 #define SAIF0			(CLKCTRL + 0x0100)  macro
59  *  DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
61  *  CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
62  *		SAIF0 clock inputs selected for SAIF1 input clocks.
63  *  EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
65  *  EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
93 	val = readl_relaxed(SAIF0);  in clk_misc_init()
95 	writel_relaxed(val, SAIF0);  in clk_misc_init()
140 	ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm,  enumerator
204 	clks[saif0_div] = mxs_clk_frac("saif0_div", "saif0_sel", SAIF0, 0, 16, 29);  in mx28_clocks_init()
220 	clks[saif0] = mxs_clk_gate("saif0", "saif0_div", SAIF0, 31);  in mx28_clocks_init()