107 	 * Source ssp clock from ref_io than ref_xtal,  in clk_misc_init()
108 	 * as ref_xtal only provides 24 MHz as maximum.  in clk_misc_init()
122 static const char *const sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
123 static const char *const sel_io0[]  __initconst = { "ref_io0", "ref_xtal", };
124 static const char *const sel_io1[]  __initconst = { "ref_io1", "ref_xtal", };
125 static const char *const sel_pix[]  __initconst = { "ref_pix", "ref_xtal", };
126 static const char *const sel_gpmi[] __initconst = { "ref_gpmi", "ref_xtal", };
127 static const char *const sel_pll0[] __initconst = { "pll0", "ref_xtal", };
130 static const char *const ptp_sels[] __initconst = { "ref_xtal", "pll0", };
133 	ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1,  enumerator
167 	clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);  in mx28_clocks_init()
168 	clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000);  in mx28_clocks_init()
169 	clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000);  in mx28_clocks_init()
170 	clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000);  in mx28_clocks_init()
191 	clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);  in mx28_clocks_init()
193 	clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);  in mx28_clocks_init()
200 	clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);  in mx28_clocks_init()
206 	clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);  in mx28_clocks_init()
207 	clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);  in mx28_clocks_init()
211 	clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);  in mx28_clocks_init()
212 	clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);  in mx28_clocks_init()
225 	clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30);  in mx28_clocks_init()
226 	clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28);  in mx28_clocks_init()