1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
15 #include "dove-divider.h"
56 	val = readl_relaxed(dc->base + DIV_CTRL0);  in dove_get_divider()
57 	val >>= dc->div_bit_start;  in dove_get_divider()
59 	divider = val & ~(~0 << dc->div_bit_size);  in dove_get_divider()
61 	if (dc->divider_table)  in dove_get_divider()
62 		divider = dc->divider_table[divider];  in dove_get_divider()
67 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate,  in dove_calc_divider()  argument
72 	divider = DIV_ROUND_CLOSEST(parent_rate, rate);  in dove_calc_divider()
74 	if (dc->divider_table) {  in dove_calc_divider()
77 		for (i = 0; dc->divider_table[i]; i++)  in dove_calc_divider()
78 			if (divider == dc->divider_table[i]) {  in dove_calc_divider()
83 		if (!dc->divider_table[i])  in dove_calc_divider()
84 			return -EINVAL;  in dove_calc_divider()
86 		max = 1 << dc->div_bit_size;  in dove_calc_divider()
89 			return -EINVAL;  in dove_calc_divider()
91 			divider = max - 1;  in dove_calc_divider()
99 static unsigned long dove_recalc_rate(struct clk_hw *hw, unsigned long parent)  in dove_recalc_rate()  argument
103 	unsigned long rate = DIV_ROUND_CLOSEST(parent, divider);  in dove_recalc_rate()  local
105 	pr_debug("%s(): %s divider=%u parent=%lu rate=%lu\n",  in dove_recalc_rate()
106 		 __func__, dc->name, divider, parent, rate);  in dove_recalc_rate()
108 	return rate;  in dove_recalc_rate()
111 static long dove_round_rate(struct clk_hw *hw, unsigned long rate,  in dove_round_rate()  argument
112 			    unsigned long *parent)  in dove_round_rate()  argument
115 	unsigned long parent_rate = *parent;  in dove_round_rate()
118 	divider = dove_calc_divider(dc, rate, parent_rate, false);  in dove_round_rate()
122 	rate = DIV_ROUND_CLOSEST(parent_rate, divider);  in dove_round_rate()
124 	pr_debug("%s(): %s divider=%u parent=%lu rate=%lu\n",  in dove_round_rate()
125 		 __func__, dc->name, divider, parent_rate, rate);  in dove_round_rate()
127 	return rate;  in dove_round_rate()
130 static int dove_set_clock(struct clk_hw *hw, unsigned long rate,  in dove_set_clock()  argument
137 	divider = dove_calc_divider(dc, rate, parent_rate, true);  in dove_set_clock()
141 	pr_debug("%s(): %s divider=%u parent=%lu rate=%lu\n",  in dove_set_clock()
142 		 __func__, dc->name, divider, parent_rate, rate);  in dove_set_clock()
144 	div = (u32)divider << dc->div_bit_start;  in dove_set_clock()
145 	mask = ~(~0 << dc->div_bit_size) << dc->div_bit_start;  in dove_set_clock()
146 	load = BIT(dc->div_bit_load);  in dove_set_clock()
148 	spin_lock(dc->lock);  in dove_set_clock()
149 	dove_load_divider(dc->base, div, mask, load);  in dove_set_clock()
150 	spin_unlock(dc->lock);  in dove_set_clock()
173 	strscpy(name, dc->name, sizeof(name));  in clk_register_dove_divider()
175 	dc->hw.init = &init;  in clk_register_dove_divider()
176 	dc->base = base;  in clk_register_dove_divider()
177 	dc->div_bit_size = dc->div_bit_end - dc->div_bit_start + 1;  in clk_register_dove_divider()
179 	return clk_register(dev, &dc->hw);  in clk_register_dove_divider()
184 static u32 axi_divider[] = {-1, 2, 1, 3, 4, 6, 5, 7, 8, 10, 9, 0};
216 	"core-pll",
226 	 * Create the core PLL clock.  We treat this as a fixed rate  in dove_divider_init()