clk/mstar/clk-msc313-cpupll.c

17  * 0x140 -- LPF low. Seems to store one half of the clock transition
18  * 0x144 /
19  * 0x148 -- LPF high. Seems to store one half of the clock transition
20  * 0x14c /
21  * 0x150 -- vendor code says "toggle lpf enable"
22  * 0x154 -- mu?
23  * 0x15c -- lpf_update_count?
24  * 0x160 -- vendor code says "switch to LPF". Clock source config? Register bank?
25  * 0x164 -- vendor code says "from low to high" which seems to mean transition from LPF low to
27  * 0x174 -- Seems to be the PLL lock status bit
28  * 0x180 -- Seems to be the current frequency, this might need to be populated by software?
29  * 0x184 /  The vendor driver uses these to set the initial value of LPF low
35  * divisor 0xfb586f (220 MHz) works but 0xfb7fff locks up.
40  * 400000000  - 0x0067AE14
41  * 600000000  - 0x00451EB8,
42  * 800000000  - 0x0033D70A,
43  * 1000000000 - 0x002978d4,
46 #define REG_LPF_LOW_L		0x140
47 #define REG_LPF_LOW_H		0x144
48 #define REG_LPF_HIGH_BOTTOM	0x148
49 #define REG_LPF_HIGH_TOP	0x14c
50 #define REG_LPF_TOGGLE		0x150
51 #define REG_LPF_MYSTERYTWO	0x154
52 #define REG_LPF_UPDATE_COUNT	0x15c
53 #define REG_LPF_MYSTERYONE	0x160
54 #define REG_LPF_TRANSITIONCTRL	0x164
55 #define REG_LPF_LOCK		0x174
56 #define REG_CURRENT		0x180
83 	u16 l = value & 0xffff, h = (value >> 16) & 0xffff;  in msc313_cpupll_reg_write32()
95 	iowrite16(0x1, cpupll->base + REG_LPF_MYSTERYONE);  in msc313_cpupll_setfreq()
96 	iowrite16(0x6, cpupll->base + REG_LPF_MYSTERYTWO);  in msc313_cpupll_setfreq()
97 	iowrite16(0x8, cpupll->base + REG_LPF_UPDATE_COUNT);  in msc313_cpupll_setfreq()
100 	iowrite16(0, cpupll->base + REG_LPF_TOGGLE);  in msc313_cpupll_setfreq()
112 	iowrite16(0, cpupll->base + REG_LPF_TOGGLE);  in msc313_cpupll_setfreq()
121 	if (prescaled == 0 || reg == 0)  in msc313_cpupll_frequencyforreg()
122 		return 0;  in msc313_cpupll_frequencyforreg()
130 	if (prescaled == 0 || rate == 0)  in msc313_cpupll_regforfrequecy()
131 		return 0;  in msc313_cpupll_regforfrequecy()
153 	for (; rounded >= rate && reg > 0; reg--)  in msc313_cpupll_round_rate()
166 	return 0;  in msc313_cpupll_set_rate()
183 	struct clk_parent_data cpupll_parent = { .index	= 0 };  in msc313_cpupll_probe()
192 	cpupll->base = devm_platform_ioremap_resource(pdev, 0);  in msc313_cpupll_probe()