Lines Matching +full:0 +full:x1b
22 #define APBC_RTC 0x28
23 #define APBC_TWSI0 0x2c
24 #define APBC_KPC 0x18
25 #define APBC_UART0 0x0
26 #define APBC_UART1 0x4
27 #define APBC_GPIO 0x8
28 #define APBC_PWM0 0xc
29 #define APBC_PWM1 0x10
30 #define APBC_PWM2 0x14
31 #define APBC_PWM3 0x18
32 #define APBC_SSP0 0x1c
33 #define APBC_SSP1 0x20
34 #define APBC_SSP2 0x4c
35 #define APBC_TIMER0 0x30
36 #define APBC_TIMER1 0x44
37 #define APBCP_TWSI1 0x28
38 #define APBCP_UART2 0x1c
39 #define APMU_SDH0 0x54
40 #define APMU_SDH1 0x58
41 #define APMU_USB 0x5c
42 #define APMU_DISP0 0x4c
43 #define APMU_CCIC0 0x50
44 #define APMU_DFC 0x60
45 #define MPMU_UART_PLL 0x14
58 {PXA910_CLK_CLK32, "clk32", NULL, 0, 32768},
59 {PXA910_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
60 {PXA910_CLK_PLL1, "pll1", NULL, 0, 624000000},
61 {PXA910_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
65 {PXA910_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
66 {PXA910_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
67 {PXA910_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
68 {PXA910_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
69 {PXA910_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
70 {PXA910_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
71 {PXA910_CLK_PLL1_24, "pll1_24", "pll1_12", 1, 2, 0},
72 {PXA910_CLK_PLL1_48, "pll1_48", "pll1_24", 1, 2, 0},
73 {PXA910_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
74 {PXA910_CLK_PLL1_192, "pll1_192", "pll1_96", 1, 2, 0},
75 {PXA910_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
76 {PXA910_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
77 {PXA910_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
78 {PXA910_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
83 .num_mask = 0x1fff,
84 .den_mask = 0x1fff,
86 .den_shift = 0,
128 …{0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0…
129 …{0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1…
130 …{0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4,…
131 …{0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4,…
132 …{0, "timer0_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TI…
133 …{0, "timer1_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TI…
137 …{0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBCP_UART…
141 …{PXA910_CLK_TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, …
142 …{PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_l…
143 …{PXA910_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 0x3, 0x0, MMP_CLK_GATE_NE…
144 …{PXA910_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_…
145 …{PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_…
146 …{PXA910_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_…
147 …{PXA910_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_…
148 …{PXA910_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_…
150 …{PXA910_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 0x3, 0x0, 0, &u…
151 …{PXA910_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 0x3, 0x0, 0, &u…
152 …{PXA910_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_…
153 …{PXA910_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_…
154 …{PXA910_CLK_TIMER0, "timer0_clk", "timer0_mux", CLK_SET_RATE_PARENT, APBC_TIMER0, 0x3, 0x3, 0x0, 0…
155 …{PXA910_CLK_TIMER1, "timer1_clk", "timer1_mux", CLK_SET_RATE_PARENT, APBC_TIMER1, 0x3, 0x3, 0x0, 0…
159 …{PXA910_CLK_TWSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBCP_TWSI1, 0x3, 0x3, 0x0, 0,…
161 …{PXA910_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_UART2, 0x3, 0x3, 0x0, 0, &…
195 …{0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6,…
196 …{0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6,…
197 …{0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0…
198 …{0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0…
199 …{0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT…
203 {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
207 {PXA910_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
208 {PXA910_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
209 {PXA910_CLK_SPH, "sph_clk", "usb_pll", 0, APMU_USB, 0x12, 0x12, 0x0, 0, &usb_lock},
211 …{PXA910_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh…
212 …{PXA910_CLK_SDH1, "sdh1_clk", "sdh1_mux", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh…
213 …{PXA910_CLK_DISP0, "disp0_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, …
214 …{PXA910_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, …
215 …"ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock…
216 …ic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_loc…
246 base = 0; in pxa910_clk_reset_init()
247 for (i = 0; i < nr_resets_apbc; i++) { in pxa910_clk_reset_init()
251 cells[base + i].flags = 0; in pxa910_clk_reset_init()
253 cells[base + i].bits = 0x4; in pxa910_clk_reset_init()
257 for (i = 0; i < nr_resets_apbcp; i++) { in pxa910_clk_reset_init()
261 cells[base + i].flags = 0; in pxa910_clk_reset_init()
263 cells[base + i].bits = 0x4; in pxa910_clk_reset_init()
277 pxa_unit->mpmu_base = of_iomap(np, 0); in pxa910_clk_init()