1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/clock/microchip,pic32-clock.h>
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
17 #include "clk-core.h"
81 	.slew_div = 2, /* step of div_4 -> div_2 -> no_div */
128 	struct clk *clks[MAXCLKS];
129 	struct pic32_clk_common core;  member
142 	if (readl(cd->core.iobase) & BIT(2))  in pic32_fscm_nmi()
143 		pr_alert("pic32-clk: FSCM detected clk failure.\n");  in pic32_fscm_nmi()
153 	struct device_node *np = pdev->dev.of_node;  in pic32mzda_clk_probe()
155 	struct pic32_clk_common *core;  in pic32mzda_clk_probe()  local
156 	struct clk *pll_mux_clk, *clk;  in pic32mzda_clk_probe()  local
157 	struct clk **clks;  in pic32mzda_clk_probe()
160 	cd = devm_kzalloc(&pdev->dev, sizeof(*cd), GFP_KERNEL);  in pic32mzda_clk_probe()
162 		return -ENOMEM;  in pic32mzda_clk_probe()
164 	core = &cd->core;  in pic32mzda_clk_probe()
165 	core->iobase = of_io_request_and_map(np, 0, of_node_full_name(np));  in pic32mzda_clk_probe()
166 	if (IS_ERR(core->iobase)) {  in pic32mzda_clk_probe()
167 		dev_err(&pdev->dev, "pic32-clk: failed to map registers\n");  in pic32mzda_clk_probe()
168 		return PTR_ERR(core->iobase);  in pic32mzda_clk_probe()
171 	spin_lock_init(&core->reg_lock);  in pic32mzda_clk_probe()
172 	core->dev = &pdev->dev;  in pic32mzda_clk_probe()
173 	clks = &cd->clks[0];  in pic32mzda_clk_probe()
176 	clks[POSCCLK] = clk_register_fixed_rate(&pdev->dev, "posc_clk", NULL,  in pic32mzda_clk_probe()
178 	clks[FRCCLK] =  clk_register_fixed_rate(&pdev->dev, "frc_clk", NULL,  in pic32mzda_clk_probe()
180 	clks[BFRCCLK] = clk_register_fixed_rate(&pdev->dev, "bfrc_clk", NULL,  in pic32mzda_clk_probe()
182 	clks[LPRCCLK] = clk_register_fixed_rate(&pdev->dev, "lprc_clk", NULL,  in pic32mzda_clk_probe()
184 	clks[UPLLCLK] = clk_register_fixed_rate(&pdev->dev, "usbphy_clk", NULL,  in pic32mzda_clk_probe()
187 	if (of_property_read_bool(np, "microchip,pic32mzda-sosc")) {  in pic32mzda_clk_probe()
188 		pr_info("pic32-clk: dt requests SOSC.\n");  in pic32mzda_clk_probe()
189 		clks[SOSCCLK] = pic32_sosc_clk_register(&sosc_clk, core);  in pic32mzda_clk_probe()
192 	clks[FRCDIVCLK] = clk_register_divider(&pdev->dev, "frcdiv_clk",  in pic32mzda_clk_probe()
194 					       core->iobase,  in pic32mzda_clk_probe()
198 					       &core->reg_lock);  in pic32mzda_clk_probe()
200 	pll_mux_clk = clk_register_mux(&pdev->dev, "spll_mux_clk",  in pic32mzda_clk_probe()
202 				       core->iobase + 0x020,  in pic32mzda_clk_probe()
203 				       PLL_ICLK_SHIFT, 1, 0, &core->reg_lock);  in pic32mzda_clk_probe()
205 		pr_err("spll_mux_clk: clk register failed\n");  in pic32mzda_clk_probe()
208 	clks[PLLCLK] = pic32_spll_clk_register(&sys_pll, core);  in pic32mzda_clk_probe()
210 	clks[SCLK] = pic32_sys_clk_register(&sys_mux_clk, core);  in pic32mzda_clk_probe()
214 							  core);  in pic32mzda_clk_probe()
217 		clks[nr_clks] = pic32_refo_clk_register(&ref_clks[i], core);  in pic32mzda_clk_probe()
227 	cd->onecell_data.clks = clks;  in pic32mzda_clk_probe()
228 	cd->onecell_data.clk_num = MAXCLKS;  in pic32mzda_clk_probe()
230 				  &cd->onecell_data);  in pic32mzda_clk_probe()
236 		clk = clks[pic32mzda_critical_clks[i]];  in pic32mzda_clk_probe()
237 		if (clk_prepare_enable(clk))  in pic32mzda_clk_probe()
238 			dev_err(&pdev->dev, "clk_prepare_enable(%s) failed\n",  in pic32mzda_clk_probe()
239 				__clk_get_name(clk));  in pic32mzda_clk_probe()
243 	cd->failsafe_notifier.notifier_call = pic32_fscm_nmi;  in pic32mzda_clk_probe()
244 	return register_nmi_notifier(&cd->failsafe_notifier);  in pic32mzda_clk_probe()
248 	{ .compatible = "microchip,pic32mzda-clk", },
256 		.name	= "clk-pic32mzda",
269 MODULE_ALIAS("platform:clk-pic32mzda");