Lines Matching full:hw
66 .hw.init = &(struct clk_init_data){
83 .hw.init = &(struct clk_init_data){
87 &g12a_fixed_pll_dco.hw
131 .hw.init = &(struct clk_init_data){
150 .hw.init = &(struct clk_init_data){
154 &g12a_sys_pll_dco.hw
190 .hw.init = &(struct clk_init_data){
209 .hw.init = &(struct clk_init_data){
213 &g12b_sys1_pll_dco.hw
225 .hw.init = &(struct clk_init_data) {
228 .parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
242 .hw.init = &(struct clk_init_data) {
246 &g12b_sys1_pll.hw
259 .hw.init = &(struct clk_init_data){
263 &g12a_sys_pll_div16_en.hw
272 .hw.init = &(struct clk_init_data){
276 &g12b_sys1_pll_div16_en.hw
285 .hw.init = &(struct clk_init_data){
288 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
298 .hw.init = &(struct clk_init_data){
302 &g12a_fclk_div2_div.hw
322 .hw.init = &(struct clk_init_data){
325 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
335 .hw.init = &(struct clk_init_data){
339 &g12a_fclk_div3_div.hw
363 .hw.init = &(struct clk_init_data){
368 { .hw = &g12a_fclk_div2.hw },
369 { .hw = &g12a_fclk_div3.hw },
383 .hw.init = &(struct clk_init_data){
388 { .hw = &g12a_fclk_div2.hw },
389 { .hw = &g12a_fclk_div3.hw },
411 .hw.init = &(struct clk_init_data){
415 &g12a_cpu_clk_premux0.hw
430 .hw.init = &(struct clk_init_data){
434 &g12a_cpu_clk_premux0.hw,
435 &g12a_cpu_clk_mux0_div.hw,
449 .hw.init = &(struct clk_init_data){
453 &g12a_cpu_clk_premux1.hw
466 .hw.init = &(struct clk_init_data){
470 &g12a_cpu_clk_premux1.hw,
471 &g12a_cpu_clk_mux1_div.hw,
487 .hw.init = &(struct clk_init_data){
491 &g12a_cpu_clk_postmux0.hw,
492 &g12a_cpu_clk_postmux1.hw,
507 .hw.init = &(struct clk_init_data){
511 &g12a_cpu_clk_dyn.hw,
512 &g12a_sys_pll.hw,
527 .hw.init = &(struct clk_init_data){
531 &g12a_cpu_clk_dyn.hw,
532 &g12b_sys1_pll.hw
547 .hw.init = &(struct clk_init_data){
552 { .hw = &g12a_fclk_div2.hw },
553 { .hw = &g12a_fclk_div3.hw },
574 .hw.init = &(struct clk_init_data){
578 &g12b_cpub_clk_premux0.hw
593 .hw.init = &(struct clk_init_data){
597 &g12b_cpub_clk_premux0.hw,
598 &g12b_cpub_clk_mux0_div.hw
612 .hw.init = &(struct clk_init_data){
617 { .hw = &g12a_fclk_div2.hw },
618 { .hw = &g12a_fclk_div3.hw },
633 .hw.init = &(struct clk_init_data){
637 &g12b_cpub_clk_premux1.hw
650 .hw.init = &(struct clk_init_data){
654 &g12b_cpub_clk_premux1.hw,
655 &g12b_cpub_clk_mux1_div.hw
671 .hw.init = &(struct clk_init_data){
675 &g12b_cpub_clk_postmux0.hw,
676 &g12b_cpub_clk_postmux1.hw
691 .hw.init = &(struct clk_init_data){
695 &g12b_cpub_clk_dyn.hw,
696 &g12a_sys_pll.hw
712 .hw.init = &(struct clk_init_data){
717 { .hw = &g12a_fclk_div2.hw },
718 { .hw = &g12a_fclk_div3.hw },
719 { .hw = &sm1_gp1_pll.hw },
732 .hw.init = &(struct clk_init_data){
737 { .hw = &g12a_fclk_div2.hw },
738 { .hw = &g12a_fclk_div3.hw },
739 { .hw = &sm1_gp1_pll.hw },
752 .hw.init = &(struct clk_init_data){
756 &sm1_dsu_clk_premux0.hw
769 .hw.init = &(struct clk_init_data){
773 &sm1_dsu_clk_premux0.hw,
774 &sm1_dsu_clk_mux0_div.hw,
787 .hw.init = &(struct clk_init_data){
791 &sm1_dsu_clk_premux1.hw
804 .hw.init = &(struct clk_init_data){
808 &sm1_dsu_clk_premux1.hw,
809 &sm1_dsu_clk_mux1_div.hw,
822 .hw.init = &(struct clk_init_data){
826 &sm1_dsu_clk_postmux0.hw,
827 &sm1_dsu_clk_postmux1.hw,
840 .hw.init = &(struct clk_init_data){
844 &sm1_dsu_clk_dyn.hw,
845 &g12a_sys_pll.hw,
858 .hw.init = &(struct clk_init_data){
862 &g12a_cpu_clk.hw,
876 .hw.init = &(struct clk_init_data){
880 &g12a_cpu_clk.hw,
894 .hw.init = &(struct clk_init_data){
898 &g12a_cpu_clk.hw,
912 .hw.init = &(struct clk_init_data){
916 &g12a_cpu_clk.hw,
917 &sm1_dsu_final_clk.hw,
1029 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1030 .cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
1031 .cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
1032 .cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
1037 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1038 .cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
1039 .cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
1040 .cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
1112 .sys_pll = &g12a_sys_pll.hw,
1113 .cpu_clk = &g12a_cpu_clk.hw,
1114 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1120 .sys_pll = &g12b_sys1_pll.hw,
1121 .cpu_clk = &g12b_cpu_clk.hw,
1122 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1128 .sys_pll = &g12a_sys_pll.hw,
1129 .cpu_clk = &g12b_cpub_clk.hw,
1130 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1139 .hw.init = &(struct clk_init_data) {
1143 &g12a_cpu_clk.hw
1158 .hw.init = &(struct clk_init_data) {
1162 &g12b_cpub_clk.hw
1175 .hw.init = &(struct clk_init_data){
1179 &g12a_cpu_clk_div16_en.hw
1188 .hw.init = &(struct clk_init_data){
1192 &g12b_cpub_clk_div16_en.hw
1205 .hw.init = &(struct clk_init_data){
1208 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1218 .hw.init = &(struct clk_init_data) {
1222 &g12a_cpu_clk_apb_div.hw
1239 .hw.init = &(struct clk_init_data){
1242 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1252 .hw.init = &(struct clk_init_data) {
1256 &g12a_cpu_clk_atb_div.hw
1273 .hw.init = &(struct clk_init_data){
1276 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1286 .hw.init = &(struct clk_init_data) {
1290 &g12a_cpu_clk_axi_div.hw
1307 .hw.init = &(struct clk_init_data){
1330 .hw.init = &(struct clk_init_data) {
1334 &g12a_cpu_clk_trace_div.hw
1347 .hw.init = &(struct clk_init_data){
1351 &g12b_cpub_clk.hw
1360 .hw.init = &(struct clk_init_data){
1364 &g12b_cpub_clk.hw
1373 .hw.init = &(struct clk_init_data){
1377 &g12b_cpub_clk.hw
1386 .hw.init = &(struct clk_init_data){
1390 &g12b_cpub_clk.hw
1399 .hw.init = &(struct clk_init_data){
1403 &g12b_cpub_clk.hw
1412 .hw.init = &(struct clk_init_data){
1416 &g12b_cpub_clk.hw
1425 .hw.init = &(struct clk_init_data){
1429 &g12b_cpub_clk.hw
1443 .hw.init = &(struct clk_init_data){
1447 &g12b_cpub_clk_div2.hw,
1448 &g12b_cpub_clk_div3.hw,
1449 &g12b_cpub_clk_div4.hw,
1450 &g12b_cpub_clk_div5.hw,
1451 &g12b_cpub_clk_div6.hw,
1452 &g12b_cpub_clk_div7.hw,
1453 &g12b_cpub_clk_div8.hw
1465 .hw.init = &(struct clk_init_data) {
1469 &g12b_cpub_clk_apb_sel.hw
1486 .hw.init = &(struct clk_init_data){
1490 &g12b_cpub_clk_div2.hw,
1491 &g12b_cpub_clk_div3.hw,
1492 &g12b_cpub_clk_div4.hw,
1493 &g12b_cpub_clk_div5.hw,
1494 &g12b_cpub_clk_div6.hw,
1495 &g12b_cpub_clk_div7.hw,
1496 &g12b_cpub_clk_div8.hw
1508 .hw.init = &(struct clk_init_data) {
1512 &g12b_cpub_clk_atb_sel.hw
1529 .hw.init = &(struct clk_init_data){
1533 &g12b_cpub_clk_div2.hw,
1534 &g12b_cpub_clk_div3.hw,
1535 &g12b_cpub_clk_div4.hw,
1536 &g12b_cpub_clk_div5.hw,
1537 &g12b_cpub_clk_div6.hw,
1538 &g12b_cpub_clk_div7.hw,
1539 &g12b_cpub_clk_div8.hw
1551 .hw.init = &(struct clk_init_data) {
1555 &g12b_cpub_clk_axi_sel.hw
1572 .hw.init = &(struct clk_init_data){
1576 &g12b_cpub_clk_div2.hw,
1577 &g12b_cpub_clk_div3.hw,
1578 &g12b_cpub_clk_div4.hw,
1579 &g12b_cpub_clk_div5.hw,
1580 &g12b_cpub_clk_div6.hw,
1581 &g12b_cpub_clk_div7.hw,
1582 &g12b_cpub_clk_div8.hw
1594 .hw.init = &(struct clk_init_data) {
1598 &g12b_cpub_clk_trace_sel.hw
1661 .hw.init = &(struct clk_init_data){
1679 .hw.init = &(struct clk_init_data){
1683 &g12a_gp0_pll_dco.hw
1723 .hw.init = &(struct clk_init_data){
1743 .hw.init = &(struct clk_init_data){
1747 &sm1_gp1_pll_dco.hw
1802 .hw.init = &(struct clk_init_data){
1820 .hw.init = &(struct clk_init_data){
1824 &g12a_hifi_pll_dco.hw
1893 .hw.init = &(struct clk_init_data){
1906 .hw.init = &(struct clk_init_data){
1910 &g12a_pcie_pll_dco.hw
1926 .hw.init = &(struct clk_init_data){
1930 &g12a_pcie_pll_dco_div2.hw
1940 .hw.init = &(struct clk_init_data){
1944 &g12a_pcie_pll_od.hw
1984 .hw.init = &(struct clk_init_data){
2006 .hw.init = &(struct clk_init_data){
2010 &g12a_hdmi_pll_dco.hw
2024 .hw.init = &(struct clk_init_data){
2028 &g12a_hdmi_pll_od.hw
2042 .hw.init = &(struct clk_init_data){
2046 &g12a_hdmi_pll_od2.hw
2056 .hw.init = &(struct clk_init_data){
2059 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2069 .hw.init = &(struct clk_init_data){
2073 &g12a_fclk_div4_div.hw
2082 .hw.init = &(struct clk_init_data){
2085 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2095 .hw.init = &(struct clk_init_data){
2099 &g12a_fclk_div5_div.hw
2108 .hw.init = &(struct clk_init_data){
2111 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2121 .hw.init = &(struct clk_init_data){
2125 &g12a_fclk_div7_div.hw
2134 .hw.init = &(struct clk_init_data){
2138 &g12a_fixed_pll_dco.hw
2149 .hw.init = &(struct clk_init_data){
2153 &g12a_fclk_div2p5_div.hw
2162 .hw.init = &(struct clk_init_data){
2166 &g12a_fixed_pll_dco.hw
2178 .hw.init = &(struct clk_init_data){
2183 { .hw = &g12a_mpll_50m_div.hw },
2192 .hw.init = &(struct clk_init_data){
2196 &g12a_fixed_pll_dco.hw
2232 .hw.init = &(struct clk_init_data){
2236 &g12a_mpll_prediv.hw
2247 .hw.init = &(struct clk_init_data){
2250 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
2286 .hw.init = &(struct clk_init_data){
2290 &g12a_mpll_prediv.hw
2301 .hw.init = &(struct clk_init_data){
2304 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
2340 .hw.init = &(struct clk_init_data){
2344 &g12a_mpll_prediv.hw
2355 .hw.init = &(struct clk_init_data){
2358 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
2394 .hw.init = &(struct clk_init_data){
2398 &g12a_mpll_prediv.hw
2409 .hw.init = &(struct clk_init_data){
2412 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
2421 { .hw = &g12a_fclk_div7.hw },
2422 { .hw = &g12a_mpll1.hw },
2423 { .hw = &g12a_mpll2.hw },
2424 { .hw = &g12a_fclk_div4.hw },
2425 { .hw = &g12a_fclk_div3.hw },
2426 { .hw = &g12a_fclk_div5.hw },
2436 .hw.init = &(struct clk_init_data){
2450 .hw.init = &(struct clk_init_data){
2454 &g12a_mpeg_clk_sel.hw
2466 .hw.init = &(struct clk_init_data){
2470 &g12a_mpeg_clk_div.hw
2479 { .hw = &g12a_fclk_div2.hw },
2480 { .hw = &g12a_fclk_div3.hw },
2481 { .hw = &g12a_fclk_div5.hw },
2482 { .hw = &g12a_fclk_div7.hw },
2498 .hw.init = &(struct clk_init_data) {
2513 .hw.init = &(struct clk_init_data) {
2517 &g12a_sd_emmc_a_clk0_sel.hw
2529 .hw.init = &(struct clk_init_data){
2533 &g12a_sd_emmc_a_clk0_div.hw
2547 .hw.init = &(struct clk_init_data) {
2562 .hw.init = &(struct clk_init_data) {
2566 &g12a_sd_emmc_b_clk0_sel.hw
2578 .hw.init = &(struct clk_init_data){
2582 &g12a_sd_emmc_b_clk0_div.hw
2596 .hw.init = &(struct clk_init_data) {
2611 .hw.init = &(struct clk_init_data) {
2615 &g12a_sd_emmc_c_clk0_sel.hw
2627 .hw.init = &(struct clk_init_data){
2631 &g12a_sd_emmc_c_clk0_div.hw
2653 .hw.init = &(struct clk_init_data) {
2656 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
2663 &g12a_vid_pll_div.hw,
2664 &g12a_hdmi_pll.hw,
2673 .hw.init = &(struct clk_init_data){
2691 .hw.init = &(struct clk_init_data) {
2695 &g12a_vid_pll_sel.hw
2705 &g12a_fclk_div3.hw,
2706 &g12a_fclk_div4.hw,
2707 &g12a_fclk_div5.hw,
2708 &g12a_fclk_div7.hw,
2709 &g12a_mpll1.hw,
2710 &g12a_vid_pll.hw,
2711 &g12a_hifi_pll.hw,
2712 &g12a_gp0_pll.hw,
2721 .hw.init = &(struct clk_init_data){
2736 .hw.init = &(struct clk_init_data){
2739 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
2750 .hw.init = &(struct clk_init_data) {
2753 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
2765 .hw.init = &(struct clk_init_data){
2780 .hw.init = &(struct clk_init_data){
2783 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
2794 .hw.init = &(struct clk_init_data) {
2797 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
2809 .hw.init = &(struct clk_init_data){
2817 &g12a_vpu_0.hw,
2818 &g12a_vpu_1.hw,
2828 &g12a_fclk_div2p5.hw,
2829 &g12a_fclk_div3.hw,
2830 &g12a_fclk_div4.hw,
2831 &g12a_fclk_div5.hw,
2832 &g12a_fclk_div7.hw,
2833 &g12a_hifi_pll.hw,
2834 &g12a_gp0_pll.hw,
2844 .hw.init = &(struct clk_init_data){
2860 .hw.init = &(struct clk_init_data){
2864 &g12a_vdec_1_sel.hw
2876 .hw.init = &(struct clk_init_data) {
2880 &g12a_vdec_1_div.hw
2894 .hw.init = &(struct clk_init_data){
2910 .hw.init = &(struct clk_init_data){
2914 &g12a_vdec_hevcf_sel.hw
2926 .hw.init = &(struct clk_init_data) {
2930 &g12a_vdec_hevcf_div.hw
2944 .hw.init = &(struct clk_init_data){
2960 .hw.init = &(struct clk_init_data){
2964 &g12a_vdec_hevc_sel.hw
2976 .hw.init = &(struct clk_init_data) {
2980 &g12a_vdec_hevc_div.hw
2990 &g12a_fclk_div4.hw,
2991 &g12a_fclk_div3.hw,
2992 &g12a_fclk_div5.hw,
2993 &g12a_fclk_div7.hw,
2994 &g12a_mpll1.hw,
2995 &g12a_vid_pll.hw,
2996 &g12a_mpll2.hw,
2997 &g12a_fclk_div2p5.hw,
3006 .hw.init = &(struct clk_init_data){
3021 .hw.init = &(struct clk_init_data){
3025 &g12a_vapb_0_sel.hw
3037 .hw.init = &(struct clk_init_data) {
3041 &g12a_vapb_0_div.hw
3054 .hw.init = &(struct clk_init_data){
3069 .hw.init = &(struct clk_init_data){
3073 &g12a_vapb_1_sel.hw
3085 .hw.init = &(struct clk_init_data) {
3089 &g12a_vapb_1_div.hw
3102 .hw.init = &(struct clk_init_data){
3110 &g12a_vapb_0.hw,
3111 &g12a_vapb_1.hw,
3123 .hw.init = &(struct clk_init_data) {
3126 .parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
3133 &g12a_vid_pll.hw,
3134 &g12a_gp0_pll.hw,
3135 &g12a_hifi_pll.hw,
3136 &g12a_mpll1.hw,
3137 &g12a_fclk_div3.hw,
3138 &g12a_fclk_div4.hw,
3139 &g12a_fclk_div5.hw,
3140 &g12a_fclk_div7.hw,
3149 .hw.init = &(struct clk_init_data){
3164 .hw.init = &(struct clk_init_data){
3178 .hw.init = &(struct clk_init_data) {
3181 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
3192 .hw.init = &(struct clk_init_data) {
3195 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
3206 .hw.init = &(struct clk_init_data){
3210 &g12a_vclk_input.hw
3236 .hw.init = &(struct clk_init_data){
3240 &g12a_vclk2_input.hw
3252 .hw.init = &(struct clk_init_data) {
3255 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
3274 .hw.init = &(struct clk_init_data) {
3277 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
3288 .hw.init = &(struct clk_init_data) {
3291 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3302 .hw.init = &(struct clk_init_data) {
3305 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3316 .hw.init = &(struct clk_init_data) {
3319 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3330 .hw.init = &(struct clk_init_data) {
3333 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3344 .hw.init = &(struct clk_init_data) {
3347 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3358 .hw.init = &(struct clk_init_data) {
3361 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3372 .hw.init = &(struct clk_init_data) {
3375 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3386 .hw.init = &(struct clk_init_data) {
3389 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3400 .hw.init = &(struct clk_init_data) {
3403 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3414 .hw.init = &(struct clk_init_data) {
3417 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3426 .hw.init = &(struct clk_init_data){
3430 &g12a_vclk_div2_en.hw
3439 .hw.init = &(struct clk_init_data){
3443 &g12a_vclk_div4_en.hw
3452 .hw.init = &(struct clk_init_data){
3456 &g12a_vclk_div6_en.hw
3465 .hw.init = &(struct clk_init_data){
3469 &g12a_vclk_div12_en.hw
3478 .hw.init = &(struct clk_init_data){
3482 &g12a_vclk2_div2_en.hw
3492 .hw.init = &(struct clk_init_data){
3496 &g12a_vclk2_div4_en.hw
3506 .hw.init = &(struct clk_init_data){
3510 &g12a_vclk2_div6_en.hw
3520 .hw.init = &(struct clk_init_data){
3524 &g12a_vclk2_div12_en.hw
3533 &g12a_vclk_div1.hw,
3534 &g12a_vclk_div2.hw,
3535 &g12a_vclk_div4.hw,
3536 &g12a_vclk_div6.hw,
3537 &g12a_vclk_div12.hw,
3538 &g12a_vclk2_div1.hw,
3539 &g12a_vclk2_div2.hw,
3540 &g12a_vclk2_div4.hw,
3541 &g12a_vclk2_div6.hw,
3542 &g12a_vclk2_div12.hw,
3552 .hw.init = &(struct clk_init_data){
3568 .hw.init = &(struct clk_init_data){
3584 .hw.init = &(struct clk_init_data){
3600 .hw.init = &(struct clk_init_data){
3612 &g12a_vclk_div1.hw,
3613 &g12a_vclk_div2.hw,
3614 &g12a_vclk_div4.hw,
3615 &g12a_vclk_div6.hw,
3616 &g12a_vclk_div12.hw,
3617 &g12a_vclk2_div1.hw,
3618 &g12a_vclk2_div2.hw,
3619 &g12a_vclk2_div4.hw,
3620 &g12a_vclk2_div6.hw,
3621 &g12a_vclk2_div12.hw,
3631 .hw.init = &(struct clk_init_data){
3645 .hw.init = &(struct clk_init_data) {
3649 &g12a_cts_enci_sel.hw
3661 .hw.init = &(struct clk_init_data) {
3665 &g12a_cts_encp_sel.hw
3677 .hw.init = &(struct clk_init_data) {
3681 &g12a_cts_encl_sel.hw
3693 .hw.init = &(struct clk_init_data) {
3697 &g12a_cts_vdac_sel.hw
3709 .hw.init = &(struct clk_init_data) {
3713 &g12a_hdmi_tx_sel.hw
3723 &g12a_vid_pll.hw,
3724 &g12a_gp0_pll.hw,
3725 &g12a_hifi_pll.hw,
3726 &g12a_mpll1.hw,
3727 &g12a_fclk_div2.hw,
3728 &g12a_fclk_div2p5.hw,
3729 &g12a_fclk_div3.hw,
3730 &g12a_fclk_div7.hw,
3740 .hw.init = &(struct clk_init_data){
3766 .hw.init = &(struct clk_init_data){
3770 &g12a_mipi_dsi_pxclk_sel.hw
3782 .hw.init = &(struct clk_init_data) {
3786 &g12a_mipi_dsi_pxclk_div.hw
3797 { .hw = &g12a_gp0_pll.hw },
3798 { .hw = &g12a_hifi_pll.hw },
3799 { .hw = &g12a_fclk_div2p5.hw },
3800 { .hw = &g12a_fclk_div3.hw },
3801 { .hw = &g12a_fclk_div4.hw },
3802 { .hw = &g12a_fclk_div5.hw },
3803 { .hw = &g12a_fclk_div7.hw },
3812 .hw.init = &(struct clk_init_data){
3826 .hw.init = &(struct clk_init_data){
3830 &g12b_mipi_isp_sel.hw
3842 .hw.init = &(struct clk_init_data) {
3846 &g12b_mipi_isp_div.hw
3857 { .hw = &g12a_fclk_div4.hw },
3858 { .hw = &g12a_fclk_div3.hw },
3859 { .hw = &g12a_fclk_div5.hw },
3869 .hw.init = &(struct clk_init_data){
3884 .hw.init = &(struct clk_init_data){
3887 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
3898 .hw.init = &(struct clk_init_data) {
3901 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
3915 { .hw = &g12a_gp0_pll.hw },
3916 { .hw = &g12a_hifi_pll.hw },
3917 { .hw = &g12a_fclk_div2p5.hw },
3918 { .hw = &g12a_fclk_div3.hw },
3919 { .hw = &g12a_fclk_div4.hw },
3920 { .hw = &g12a_fclk_div5.hw },
3921 { .hw = &g12a_fclk_div7.hw },
3930 .hw.init = &(struct clk_init_data){
3951 .hw.init = &(struct clk_init_data){
3955 &g12a_mali_0_sel.hw
3967 .hw.init = &(struct clk_init_data){
3971 &g12a_mali_0_div.hw
3984 .hw.init = &(struct clk_init_data){
4005 .hw.init = &(struct clk_init_data){
4009 &g12a_mali_1_sel.hw
4021 .hw.init = &(struct clk_init_data){
4025 &g12a_mali_1_div.hw
4033 &g12a_mali_0.hw,
4034 &g12a_mali_1.hw,
4043 .hw.init = &(struct clk_init_data){
4058 .hw.init = &(struct clk_init_data){
4073 .hw.init = &(struct clk_init_data){
4077 &g12a_ts_div.hw
4087 { .hw = &g12a_clk81.hw },
4088 { .hw = &g12a_fclk_div4.hw },
4089 { .hw = &g12a_fclk_div3.hw },
4090 { .hw = &g12a_fclk_div5.hw },
4091 { .hw = &g12a_fclk_div7.hw },
4100 .hw.init = &(struct clk_init_data){
4114 .hw.init = &(struct clk_init_data){
4118 &g12a_spicc0_sclk_sel.hw
4130 .hw.init = &(struct clk_init_data){
4134 &g12a_spicc0_sclk_div.hw
4147 .hw.init = &(struct clk_init_data){
4161 .hw.init = &(struct clk_init_data){
4165 &g12a_spicc1_sclk_sel.hw
4177 .hw.init = &(struct clk_init_data){
4181 &g12a_spicc1_sclk_div.hw
4192 { .hw = &g12a_gp0_pll.hw, },
4193 { .hw = &g12a_hifi_pll.hw, },
4194 { .hw = &g12a_fclk_div2p5.hw, },
4195 { .hw = &g12a_fclk_div3.hw, },
4196 { .hw = &g12a_fclk_div4.hw, },
4197 { .hw = &g12a_fclk_div5.hw, },
4198 { .hw = &g12a_fclk_div7.hw },
4207 .hw.init = &(struct clk_init_data){
4221 .hw.init = &(struct clk_init_data){
4225 &sm1_nna_axi_clk_sel.hw
4237 .hw.init = &(struct clk_init_data){
4241 &sm1_nna_axi_clk_div.hw
4254 .hw.init = &(struct clk_init_data){
4268 .hw.init = &(struct clk_init_data){
4272 &sm1_nna_core_clk_sel.hw
4284 .hw.init = &(struct clk_init_data){
4288 &sm1_nna_core_clk_div.hw
4296 MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
4299 MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
4381 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4382 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4383 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4384 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4385 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4386 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4387 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4388 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4389 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4390 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4391 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4392 [CLKID_CLK81] = &g12a_clk81.hw,
4393 [CLKID_MPLL0] = &g12a_mpll0.hw,
4394 [CLKID_MPLL1] = &g12a_mpll1.hw,
4395 [CLKID_MPLL2] = &g12a_mpll2.hw,
4396 [CLKID_MPLL3] = &g12a_mpll3.hw,
4397 [CLKID_DDR] = &g12a_ddr.hw,
4398 [CLKID_DOS] = &g12a_dos.hw,
4399 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4400 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4401 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4402 [CLKID_ISA] = &g12a_isa.hw,
4403 [CLKID_PL301] = &g12a_pl301.hw,
4404 [CLKID_PERIPHS] = &g12a_periphs.hw,
4405 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4406 [CLKID_I2C] = &g12a_i2c.hw,
4407 [CLKID_SANA] = &g12a_sana.hw,
4408 [CLKID_SD] = &g12a_sd.hw,
4409 [CLKID_RNG0] = &g12a_rng0.hw,
4410 [CLKID_UART0] = &g12a_uart0.hw,
4411 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4412 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4413 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4414 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4415 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4416 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4417 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4418 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4419 [CLKID_AUDIO] = &g12a_audio.hw,
4420 [CLKID_ETH] = &g12a_eth_core.hw,
4421 [CLKID_DEMUX] = &g12a_demux.hw,
4422 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4423 [CLKID_ADC] = &g12a_adc.hw,
4424 [CLKID_UART1] = &g12a_uart1.hw,
4425 [CLKID_G2D] = &g12a_g2d.hw,
4426 [CLKID_RESET] = &g12a_reset.hw,
4427 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4428 [CLKID_PARSER] = &g12a_parser.hw,
4429 [CLKID_USB] = &g12a_usb_general.hw,
4430 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4431 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4432 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4433 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4434 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4435 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4436 [CLKID_BT656] = &g12a_bt656.hw,
4437 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4438 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4439 [CLKID_UART2] = &g12a_uart2.hw,
4440 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4441 [CLKID_GIC] = &g12a_gic.hw,
4442 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4443 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4444 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4445 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4446 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4447 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4448 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4449 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4450 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4451 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4452 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4453 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4454 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4455 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4456 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4457 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4458 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4459 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4460 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4461 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4462 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4463 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4464 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4465 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4466 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4467 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4468 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4469 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4470 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4471 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4472 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4473 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4474 [CLKID_ENC480P] = &g12a_enc480p.hw,
4475 [CLKID_RNG1] = &g12a_rng1.hw,
4476 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4477 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4478 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4479 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4480 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4481 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4482 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4483 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4484 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4485 [CLKID_DMA] = &g12a_dma.hw,
4486 [CLKID_EFUSE] = &g12a_efuse.hw,
4487 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4488 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4489 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4490 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4491 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4492 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4493 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4494 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4495 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4496 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4497 [CLKID_VPU] = &g12a_vpu.hw,
4498 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4499 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4500 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4501 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4502 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4503 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4504 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4505 [CLKID_VAPB] = &g12a_vapb.hw,
4506 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4507 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4508 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4509 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4510 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4511 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4512 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4513 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4514 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4515 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4516 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4517 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4518 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4519 [CLKID_VCLK] = &g12a_vclk.hw,
4520 [CLKID_VCLK2] = &g12a_vclk2.hw,
4521 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4522 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4523 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4524 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4525 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4526 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4527 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4528 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4529 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4530 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4531 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4532 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4533 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4534 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4535 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4536 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4537 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4538 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4539 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4540 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4541 [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
4542 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4543 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4544 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4545 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4546 [CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
4547 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4548 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4549 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4550 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4551 [CLKID_HDMI] = &g12a_hdmi.hw,
4552 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4553 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4554 [CLKID_MALI_0] = &g12a_mali_0.hw,
4555 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4556 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4557 [CLKID_MALI_1] = &g12a_mali_1.hw,
4558 [CLKID_MALI] = &g12a_mali.hw,
4559 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4560 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4561 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4562 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4563 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4564 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4565 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4566 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4567 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4568 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4569 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4570 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
4571 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4572 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4573 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4574 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4575 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4576 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4577 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4578 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4579 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4580 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4581 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4582 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4583 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4584 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4585 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4586 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4587 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4588 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4589 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4590 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4591 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4592 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4593 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4594 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4595 [CLKID_TS] = &g12a_ts.hw,
4596 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4597 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4598 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4599 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4600 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4601 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4602 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
4603 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
4604 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
4608 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4609 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4610 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4611 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4612 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4613 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4614 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4615 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4616 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4617 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4618 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4619 [CLKID_CLK81] = &g12a_clk81.hw,
4620 [CLKID_MPLL0] = &g12a_mpll0.hw,
4621 [CLKID_MPLL1] = &g12a_mpll1.hw,
4622 [CLKID_MPLL2] = &g12a_mpll2.hw,
4623 [CLKID_MPLL3] = &g12a_mpll3.hw,
4624 [CLKID_DDR] = &g12a_ddr.hw,
4625 [CLKID_DOS] = &g12a_dos.hw,
4626 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4627 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4628 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4629 [CLKID_ISA] = &g12a_isa.hw,
4630 [CLKID_PL301] = &g12a_pl301.hw,
4631 [CLKID_PERIPHS] = &g12a_periphs.hw,
4632 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4633 [CLKID_I2C] = &g12a_i2c.hw,
4634 [CLKID_SANA] = &g12a_sana.hw,
4635 [CLKID_SD] = &g12a_sd.hw,
4636 [CLKID_RNG0] = &g12a_rng0.hw,
4637 [CLKID_UART0] = &g12a_uart0.hw,
4638 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4639 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4640 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4641 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4642 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4643 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4644 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4645 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4646 [CLKID_AUDIO] = &g12a_audio.hw,
4647 [CLKID_ETH] = &g12a_eth_core.hw,
4648 [CLKID_DEMUX] = &g12a_demux.hw,
4649 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4650 [CLKID_ADC] = &g12a_adc.hw,
4651 [CLKID_UART1] = &g12a_uart1.hw,
4652 [CLKID_G2D] = &g12a_g2d.hw,
4653 [CLKID_RESET] = &g12a_reset.hw,
4654 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4655 [CLKID_PARSER] = &g12a_parser.hw,
4656 [CLKID_USB] = &g12a_usb_general.hw,
4657 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4658 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4659 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4660 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4661 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4662 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4663 [CLKID_BT656] = &g12a_bt656.hw,
4664 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4665 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4666 [CLKID_UART2] = &g12a_uart2.hw,
4667 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4668 [CLKID_GIC] = &g12a_gic.hw,
4669 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4670 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4671 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4672 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4673 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4674 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4675 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4676 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4677 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4678 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4679 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4680 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4681 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4682 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4683 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4684 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4685 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4686 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4687 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4688 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4689 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4690 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4691 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4692 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4693 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4694 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4695 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4696 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4697 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4698 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4699 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4700 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4701 [CLKID_ENC480P] = &g12a_enc480p.hw,
4702 [CLKID_RNG1] = &g12a_rng1.hw,
4703 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4704 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4705 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4706 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4707 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4708 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4709 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4710 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4711 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4712 [CLKID_DMA] = &g12a_dma.hw,
4713 [CLKID_EFUSE] = &g12a_efuse.hw,
4714 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4715 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4716 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4717 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4718 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4719 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4720 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4721 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4722 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4723 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4724 [CLKID_VPU] = &g12a_vpu.hw,
4725 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4726 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4727 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4728 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4729 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4730 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4731 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4732 [CLKID_VAPB] = &g12a_vapb.hw,
4733 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4734 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4735 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4736 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4737 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4738 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4739 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4740 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4741 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4742 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4743 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4744 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4745 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4746 [CLKID_VCLK] = &g12a_vclk.hw,
4747 [CLKID_VCLK2] = &g12a_vclk2.hw,
4748 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4749 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4750 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4751 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4752 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4753 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4754 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4755 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4756 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4757 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4758 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4759 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4760 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4761 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4762 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4763 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4764 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4765 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4766 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4767 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4768 [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
4769 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4770 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4771 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4772 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4773 [CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
4774 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4775 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4776 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4777 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4778 [CLKID_HDMI] = &g12a_hdmi.hw,
4779 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4780 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4781 [CLKID_MALI_0] = &g12a_mali_0.hw,
4782 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4783 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4784 [CLKID_MALI_1] = &g12a_mali_1.hw,
4785 [CLKID_MALI] = &g12a_mali.hw,
4786 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4787 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4788 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4789 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4790 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4791 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4792 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4793 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4794 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4795 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4796 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4797 [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
4798 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4799 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4800 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4801 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4802 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4803 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4804 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4805 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4806 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4807 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4808 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4809 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4810 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4811 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4812 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4813 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4814 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4815 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4816 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4817 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4818 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4819 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4820 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4821 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4822 [CLKID_TS] = &g12a_ts.hw,
4823 [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
4824 [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
4825 [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
4826 [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
4827 [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,
4828 [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,
4829 [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,
4830 [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,
4831 [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,
4832 [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,
4833 [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
4834 [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
4835 [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
4836 [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
4837 [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
4838 [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
4839 [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
4840 [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
4841 [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
4842 [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
4843 [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
4844 [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
4845 [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
4846 [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
4847 [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
4848 [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
4849 [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
4850 [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
4851 [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
4852 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4853 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4854 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4855 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4856 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4857 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4858 [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
4859 [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
4860 [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
4861 [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
4862 [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
4863 [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
4864 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
4865 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
4866 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
4867 [CLKID_MIPI_ISP_SEL] = &g12b_mipi_isp_sel.hw,
4868 [CLKID_MIPI_ISP_DIV] = &g12b_mipi_isp_div.hw,
4869 [CLKID_MIPI_ISP] = &g12b_mipi_isp.hw,
4870 [CLKID_MIPI_ISP_GATE] = &g12b_mipi_isp_gate.hw,
4871 [CLKID_MIPI_ISP_CSI_PHY0] = &g12b_csi_phy0.hw,
4872 [CLKID_MIPI_ISP_CSI_PHY1] = &g12b_csi_phy1.hw,
4876 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4877 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4878 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4879 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4880 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4881 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4882 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4883 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4884 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4885 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4886 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4887 [CLKID_CLK81] = &g12a_clk81.hw,
4888 [CLKID_MPLL0] = &g12a_mpll0.hw,
4889 [CLKID_MPLL1] = &g12a_mpll1.hw,
4890 [CLKID_MPLL2] = &g12a_mpll2.hw,
4891 [CLKID_MPLL3] = &g12a_mpll3.hw,
4892 [CLKID_DDR] = &g12a_ddr.hw,
4893 [CLKID_DOS] = &g12a_dos.hw,
4894 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4895 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4896 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4897 [CLKID_ISA] = &g12a_isa.hw,
4898 [CLKID_PL301] = &g12a_pl301.hw,
4899 [CLKID_PERIPHS] = &g12a_periphs.hw,
4900 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4901 [CLKID_I2C] = &g12a_i2c.hw,
4902 [CLKID_SANA] = &g12a_sana.hw,
4903 [CLKID_SD] = &g12a_sd.hw,
4904 [CLKID_RNG0] = &g12a_rng0.hw,
4905 [CLKID_UART0] = &g12a_uart0.hw,
4906 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4907 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4908 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4909 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4910 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4911 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4912 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4913 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4914 [CLKID_AUDIO] = &g12a_audio.hw,
4915 [CLKID_ETH] = &g12a_eth_core.hw,
4916 [CLKID_DEMUX] = &g12a_demux.hw,
4917 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4918 [CLKID_ADC] = &g12a_adc.hw,
4919 [CLKID_UART1] = &g12a_uart1.hw,
4920 [CLKID_G2D] = &g12a_g2d.hw,
4921 [CLKID_RESET] = &g12a_reset.hw,
4922 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4923 [CLKID_PARSER] = &g12a_parser.hw,
4924 [CLKID_USB] = &g12a_usb_general.hw,
4925 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4926 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4927 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4928 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4929 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4930 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4931 [CLKID_BT656] = &g12a_bt656.hw,
4932 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4933 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4934 [CLKID_UART2] = &g12a_uart2.hw,
4935 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4936 [CLKID_GIC] = &g12a_gic.hw,
4937 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4938 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4939 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4940 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4941 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4942 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4943 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4944 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4945 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4946 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4947 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4948 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4949 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4950 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4951 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4952 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4953 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4954 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4955 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4956 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4957 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4958 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4959 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4960 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4961 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4962 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4963 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4964 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4965 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4966 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4967 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4968 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4969 [CLKID_ENC480P] = &g12a_enc480p.hw,
4970 [CLKID_RNG1] = &g12a_rng1.hw,
4971 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4972 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4973 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4974 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4975 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4976 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4977 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4978 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4979 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4980 [CLKID_DMA] = &g12a_dma.hw,
4981 [CLKID_EFUSE] = &g12a_efuse.hw,
4982 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4983 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4984 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4985 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4986 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4987 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4988 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4989 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4990 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4991 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4992 [CLKID_VPU] = &g12a_vpu.hw,
4993 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4994 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4995 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4996 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4997 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4998 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4999 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
5000 [CLKID_VAPB] = &g12a_vapb.hw,
5001 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
5002 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
5003 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
5004 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
5005 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
5006 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
5007 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
5008 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
5009 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
5010 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
5011 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
5012 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
5013 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
5014 [CLKID_VCLK] = &g12a_vclk.hw,
5015 [CLKID_VCLK2] = &g12a_vclk2.hw,
5016 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
5017 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
5018 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
5019 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
5020 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
5021 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
5022 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
5023 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
5024 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
5025 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
5026 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
5027 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
5028 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
5029 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
5030 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
5031 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
5032 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
5033 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
5034 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
5035 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
5036 [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
5037 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
5038 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
5039 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
5040 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
5041 [CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
5042 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
5043 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
5044 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
5045 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
5046 [CLKID_HDMI] = &g12a_hdmi.hw,
5047 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
5048 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
5049 [CLKID_MALI_0] = &g12a_mali_0.hw,
5050 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
5051 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
5052 [CLKID_MALI_1] = &g12a_mali_1.hw,
5053 [CLKID_MALI] = &g12a_mali.hw,
5054 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
5055 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
5056 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
5057 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
5058 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
5059 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
5060 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
5061 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
5062 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
5063 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
5064 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
5065 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
5066 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
5067 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
5068 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
5069 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
5070 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
5071 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
5072 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
5073 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
5074 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
5075 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
5076 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
5077 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
5078 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
5079 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
5080 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
5081 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
5082 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
5083 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
5084 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
5085 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
5086 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
5087 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
5088 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
5089 [CLKID_TS_DIV] = &g12a_ts_div.hw,
5090 [CLKID_TS] = &g12a_ts.hw,
5091 [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
5092 [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
5093 [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
5094 [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
5095 [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
5096 [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
5097 [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
5098 [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
5099 [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
5100 [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
5101 [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
5102 [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
5103 [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
5104 [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
5105 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
5106 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
5107 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
5108 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
5109 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
5110 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
5111 [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
5112 [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
5113 [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
5114 [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
5115 [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
5116 [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
5117 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
5118 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
5119 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
5394 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_postmux0.hw, in meson_g12a_dvfs_setup_common()
5404 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_dyn.hw, in meson_g12a_dvfs_setup_common()
5431 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpu_clk.hw, in meson_g12b_dvfs_setup()
5441 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_sys1_pll.hw, in meson_g12b_dvfs_setup()
5454 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_postmux0.hw, in meson_g12b_dvfs_setup()
5464 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn.hw, "dvfs"); in meson_g12b_dvfs_setup()
5473 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk.hw, DVFS_CON_ID); in meson_g12b_dvfs_setup()
5482 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID); in meson_g12b_dvfs_setup()
5505 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk.hw, DVFS_CON_ID); in meson_g12a_dvfs_setup()
5514 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID); in meson_g12a_dvfs_setup()