1 // SPDX-License-Identifier: GPL-2.0
9  * The AO Domain embeds a dual/divider to generate a more precise
10  * 32,768KHz clock for low-power suspend mode and CEC.
13  *    | Div1 |-| Cnt1 |
15  * -|  ______   ______  X--> Out
17  *    | Div2 |-| Cnt2 |
20  * The dividing can be switched to single or dual, with a counter
21  * for each divider to set when the switching is done.
24 #include <linux/clk-provider.h>
27 #include "clk-regmap.h"
28 #include "clk-dualdiv.h"
33 	return (struct meson_clk_dualdiv_data *)clk->data;  in meson_clk_dualdiv_data()
40 	if (!p->dual)  in __dualdiv_param_to_rate()
41 		return DIV_ROUND_CLOSEST(parent_rate, p->n1);  in __dualdiv_param_to_rate()
43 	return DIV_ROUND_CLOSEST(parent_rate * (p->m1 + p->m2),  in __dualdiv_param_to_rate()
44 				 p->n1 * p->m1 + p->n2 * p->m2);  in __dualdiv_param_to_rate()
54 	setting.dual = meson_parm_read(clk->map, &dualdiv->dual);  in meson_clk_dualdiv_recalc_rate()
55 	setting.n1 = meson_parm_read(clk->map, &dualdiv->n1) + 1;  in meson_clk_dualdiv_recalc_rate()
56 	setting.m1 = meson_parm_read(clk->map, &dualdiv->m1) + 1;  in meson_clk_dualdiv_recalc_rate()
57 	setting.n2 = meson_parm_read(clk->map, &dualdiv->n2) + 1;  in meson_clk_dualdiv_recalc_rate()
58 	setting.m2 = meson_parm_read(clk->map, &dualdiv->m2) + 1;  in meson_clk_dualdiv_recalc_rate()
67 	const struct meson_clk_dualdiv_param *table = dualdiv->table;  in __dualdiv_get_setting()
80 		} else if (abs(now - rate) < abs(best - rate)) {  in __dualdiv_get_setting()
96 	setting = __dualdiv_get_setting(req->rate, req->best_parent_rate,  in meson_clk_dualdiv_determine_rate()
99 		req->rate = __dualdiv_param_to_rate(req->best_parent_rate,  in meson_clk_dualdiv_determine_rate()
102 		req->rate = meson_clk_dualdiv_recalc_rate(hw,  in meson_clk_dualdiv_determine_rate()
103 							  req->best_parent_rate);  in meson_clk_dualdiv_determine_rate()
117 		return -EINVAL;  in meson_clk_dualdiv_set_rate()
119 	meson_parm_write(clk->map, &dualdiv->dual, setting->dual);  in meson_clk_dualdiv_set_rate()
120 	meson_parm_write(clk->map, &dualdiv->n1, setting->n1 - 1);  in meson_clk_dualdiv_set_rate()
121 	meson_parm_write(clk->map, &dualdiv->m1, setting->m1 - 1);  in meson_clk_dualdiv_set_rate()
122 	meson_parm_write(clk->map, &dualdiv->n2, setting->n2 - 1);  in meson_clk_dualdiv_set_rate()
123 	meson_parm_write(clk->map, &dualdiv->m2, setting->m2 - 1);  in meson_clk_dualdiv_set_rate()
140 MODULE_DESCRIPTION("Amlogic dual divider driver");