Lines Matching full:hw
31 .hw.init = &(struct clk_init_data) { \
47 .hw.init = &(struct clk_init_data){ \
63 .hw.init = &(struct clk_init_data){ \
77 .hw.init = &(struct clk_init_data) { \
99 .hw.init = &(struct clk_init_data) { \
127 .hw.init = &(struct clk_init_data) { \
144 .hw.init = &(struct clk_init_data) { \
167 .hw.init = &(struct clk_init_data) { \
646 .hw.init = &(struct clk_init_data) {
662 .hw.init = &(struct clk_init_data) {
666 &sm1_clk81_en.hw,
678 .hw.init = &(struct clk_init_data) {
682 &sm1_sysclk_a_div.hw,
695 .hw.init = &(struct clk_init_data) {
699 &sm1_clk81_en.hw,
711 .hw.init = &(struct clk_init_data) {
715 &sm1_sysclk_b_div.hw,
723 &sm1_sysclk_a_en.hw,
724 &sm1_sysclk_b_en.hw,
733 .hw.init = &(struct clk_init_data){
834 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
835 [AUD_CLKID_PDM] = &pdm.hw,
836 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
837 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
838 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
839 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
840 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
841 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
842 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
843 [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
844 [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
845 [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
846 [AUD_CLKID_TODDR_A] = &toddr_a.hw,
847 [AUD_CLKID_TODDR_B] = &toddr_b.hw,
848 [AUD_CLKID_TODDR_C] = &toddr_c.hw,
849 [AUD_CLKID_LOOPBACK] = &loopback.hw,
850 [AUD_CLKID_SPDIFIN] = &spdifin.hw,
851 [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
852 [AUD_CLKID_RESAMPLE] = &resample.hw,
853 [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
854 [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
855 [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
856 [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
857 [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
858 [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
859 [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
860 [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
861 [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
862 [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
863 [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
864 [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
865 [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
866 [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
867 [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
868 [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
869 [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
870 [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
871 [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
872 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
873 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
874 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
875 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
876 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
877 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
878 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
879 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
880 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
881 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
882 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
883 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
884 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
885 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
886 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
887 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
888 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
889 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
890 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
891 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
892 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
893 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
894 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
895 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
896 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
897 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
898 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
899 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
900 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
901 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
902 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
903 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
904 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
905 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
906 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
907 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
908 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
909 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
910 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
911 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
912 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
913 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
914 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
915 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
916 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
917 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
918 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
919 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
920 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
921 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
922 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
923 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
924 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
925 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
926 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
927 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
928 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
929 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
930 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
931 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
932 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
933 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
934 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
935 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
936 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
937 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
938 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
939 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
940 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
941 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
942 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
943 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
944 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
945 [AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw,
946 [AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw,
947 [AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw,
948 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
949 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
950 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
951 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
952 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
953 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
954 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
963 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
964 [AUD_CLKID_PDM] = &pdm.hw,
965 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
966 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
967 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
968 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
969 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
970 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
971 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
972 [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
973 [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
974 [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
975 [AUD_CLKID_TODDR_A] = &toddr_a.hw,
976 [AUD_CLKID_TODDR_B] = &toddr_b.hw,
977 [AUD_CLKID_TODDR_C] = &toddr_c.hw,
978 [AUD_CLKID_LOOPBACK] = &loopback.hw,
979 [AUD_CLKID_SPDIFIN] = &spdifin.hw,
980 [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
981 [AUD_CLKID_RESAMPLE] = &resample.hw,
982 [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
983 [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
984 [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
985 [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
986 [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
987 [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
988 [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
989 [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
990 [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
991 [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
992 [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
993 [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
994 [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
995 [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
996 [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
997 [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
998 [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
999 [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
1000 [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
1001 [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
1002 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
1003 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
1004 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
1005 [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
1006 [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
1007 [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
1008 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
1009 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
1010 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
1011 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
1012 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
1013 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
1014 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
1015 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
1016 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
1017 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
1018 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
1019 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
1020 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
1021 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
1022 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
1023 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
1024 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
1025 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
1026 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
1027 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
1028 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
1029 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
1030 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
1031 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
1032 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
1033 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
1034 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
1035 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
1036 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
1037 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
1038 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
1039 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
1040 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
1041 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
1042 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
1043 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
1044 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
1045 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
1046 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
1047 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
1048 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
1049 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
1050 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
1051 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
1052 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
1053 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
1054 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
1055 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
1056 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
1057 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
1058 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
1059 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
1060 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
1061 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
1062 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
1063 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
1064 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
1065 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
1066 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
1067 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
1068 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
1069 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
1070 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
1071 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
1072 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
1073 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
1074 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
1075 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
1076 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
1077 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
1078 [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
1079 [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
1080 [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
1081 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
1082 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
1083 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
1084 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
1085 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
1086 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
1087 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
1088 [AUD_CLKID_TDM_MCLK_PAD0] = &g12a_tdm_mclk_pad_0.hw,
1089 [AUD_CLKID_TDM_MCLK_PAD1] = &g12a_tdm_mclk_pad_1.hw,
1090 [AUD_CLKID_TDM_LRCLK_PAD0] = &g12a_tdm_lrclk_pad_0.hw,
1091 [AUD_CLKID_TDM_LRCLK_PAD1] = &g12a_tdm_lrclk_pad_1.hw,
1092 [AUD_CLKID_TDM_LRCLK_PAD2] = &g12a_tdm_lrclk_pad_2.hw,
1093 [AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw,
1094 [AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw,
1095 [AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw,
1104 [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
1105 [AUD_CLKID_PDM] = &pdm.hw,
1106 [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
1107 [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
1108 [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
1109 [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
1110 [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
1111 [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
1112 [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
1113 [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
1114 [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
1115 [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
1116 [AUD_CLKID_TODDR_A] = &toddr_a.hw,
1117 [AUD_CLKID_TODDR_B] = &toddr_b.hw,
1118 [AUD_CLKID_TODDR_C] = &toddr_c.hw,
1119 [AUD_CLKID_LOOPBACK] = &loopback.hw,
1120 [AUD_CLKID_SPDIFIN] = &spdifin.hw,
1121 [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
1122 [AUD_CLKID_RESAMPLE] = &resample.hw,
1123 [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
1124 [AUD_CLKID_MST_A_MCLK_SEL] = &sm1_mst_a_mclk_sel.hw,
1125 [AUD_CLKID_MST_B_MCLK_SEL] = &sm1_mst_b_mclk_sel.hw,
1126 [AUD_CLKID_MST_C_MCLK_SEL] = &sm1_mst_c_mclk_sel.hw,
1127 [AUD_CLKID_MST_D_MCLK_SEL] = &sm1_mst_d_mclk_sel.hw,
1128 [AUD_CLKID_MST_E_MCLK_SEL] = &sm1_mst_e_mclk_sel.hw,
1129 [AUD_CLKID_MST_F_MCLK_SEL] = &sm1_mst_f_mclk_sel.hw,
1130 [AUD_CLKID_MST_A_MCLK_DIV] = &sm1_mst_a_mclk_div.hw,
1131 [AUD_CLKID_MST_B_MCLK_DIV] = &sm1_mst_b_mclk_div.hw,
1132 [AUD_CLKID_MST_C_MCLK_DIV] = &sm1_mst_c_mclk_div.hw,
1133 [AUD_CLKID_MST_D_MCLK_DIV] = &sm1_mst_d_mclk_div.hw,
1134 [AUD_CLKID_MST_E_MCLK_DIV] = &sm1_mst_e_mclk_div.hw,
1135 [AUD_CLKID_MST_F_MCLK_DIV] = &sm1_mst_f_mclk_div.hw,
1136 [AUD_CLKID_MST_A_MCLK] = &sm1_mst_a_mclk.hw,
1137 [AUD_CLKID_MST_B_MCLK] = &sm1_mst_b_mclk.hw,
1138 [AUD_CLKID_MST_C_MCLK] = &sm1_mst_c_mclk.hw,
1139 [AUD_CLKID_MST_D_MCLK] = &sm1_mst_d_mclk.hw,
1140 [AUD_CLKID_MST_E_MCLK] = &sm1_mst_e_mclk.hw,
1141 [AUD_CLKID_MST_F_MCLK] = &sm1_mst_f_mclk.hw,
1142 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
1143 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
1144 [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
1145 [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
1146 [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
1147 [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
1148 [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
1149 [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
1150 [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
1151 [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
1152 [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
1153 [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
1154 [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
1155 [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
1156 [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
1157 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
1158 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
1159 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
1160 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
1161 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
1162 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
1163 [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
1164 [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
1165 [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
1166 [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
1167 [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
1168 [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
1169 [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
1170 [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
1171 [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
1172 [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
1173 [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
1174 [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
1175 [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
1176 [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
1177 [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
1178 [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
1179 [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
1180 [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
1181 [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
1182 [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
1183 [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
1184 [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
1185 [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
1186 [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
1187 [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
1188 [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
1189 [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
1190 [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
1191 [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
1192 [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
1193 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
1194 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
1195 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
1196 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
1197 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
1198 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
1199 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
1200 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
1201 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
1202 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
1203 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
1204 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
1205 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
1206 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
1207 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
1208 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
1209 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
1210 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
1211 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
1212 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
1213 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
1214 [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
1215 [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
1216 [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
1217 [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
1218 [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
1219 [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
1220 [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
1221 [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
1222 [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
1223 [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
1224 [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
1225 [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
1226 [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
1227 [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
1228 [AUD_CLKID_TDM_MCLK_PAD0] = &sm1_tdm_mclk_pad_0.hw,
1229 [AUD_CLKID_TDM_MCLK_PAD1] = &sm1_tdm_mclk_pad_1.hw,
1230 [AUD_CLKID_TDM_LRCLK_PAD0] = &sm1_tdm_lrclk_pad_0.hw,
1231 [AUD_CLKID_TDM_LRCLK_PAD1] = &sm1_tdm_lrclk_pad_1.hw,
1232 [AUD_CLKID_TDM_LRCLK_PAD2] = &sm1_tdm_lrclk_pad_2.hw,
1233 [AUD_CLKID_TDM_SCLK_PAD0] = &sm1_tdm_sclk_pad_0.hw,
1234 [AUD_CLKID_TDM_SCLK_PAD1] = &sm1_tdm_sclk_pad_1.hw,
1235 [AUD_CLKID_TDM_SCLK_PAD2] = &sm1_tdm_sclk_pad_2.hw,
1236 [AUD_CLKID_TOP] = &sm1_aud_top.hw,
1237 [AUD_CLKID_TORAM] = &toram.hw,
1238 [AUD_CLKID_EQDRC] = &eqdrc.hw,
1239 [AUD_CLKID_RESAMPLE_B] = &resample_b.hw,
1240 [AUD_CLKID_TOVAD] = &tovad.hw,
1241 [AUD_CLKID_LOCKER] = &locker.hw,
1242 [AUD_CLKID_SPDIFIN_LB] = &spdifin_lb.hw,
1243 [AUD_CLKID_FRDDR_D] = &frddr_d.hw,
1244 [AUD_CLKID_TODDR_D] = &toddr_d.hw,
1245 [AUD_CLKID_LOOPBACK_B] = &loopback_b.hw,
1246 [AUD_CLKID_CLK81_EN] = &sm1_clk81_en.hw,
1247 [AUD_CLKID_SYSCLK_A_DIV] = &sm1_sysclk_a_div.hw,
1248 [AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw,
1249 [AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw,
1250 [AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw,
1251 [AUD_CLKID_EARCRX] = &earcrx.hw,
1252 [AUD_CLKID_EARCRX_CMDC_SEL] = &sm1_earcrx_cmdc_clk_sel.hw,
1253 [AUD_CLKID_EARCRX_CMDC_DIV] = &sm1_earcrx_cmdc_clk_div.hw,
1254 [AUD_CLKID_EARCRX_CMDC] = &sm1_earcrx_cmdc_clk.hw,
1255 [AUD_CLKID_EARCRX_DMAC_SEL] = &sm1_earcrx_dmac_clk_sel.hw,
1256 [AUD_CLKID_EARCRX_DMAC_DIV] = &sm1_earcrx_dmac_clk_div.hw,
1257 [AUD_CLKID_EARCRX_DMAC] = &sm1_earcrx_dmac_clk.hw,
1781 struct clk_hw *hw; in axg_audio_clkc_probe() local
1819 hw = data->hw_clks.hws[i]; in axg_audio_clkc_probe()
1821 if (!hw) in axg_audio_clkc_probe()
1824 name = hw->init->name; in axg_audio_clkc_probe()
1826 ret = devm_clk_hw_register(dev, hw); in axg_audio_clkc_probe()