clk/mediatek/clk-mt8195-apusys_pll.c

1 // SPDX-License-Identifier: GPL-2.0-only
4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
6 #include "clk-mtk.h"
7 #include "clk-pll.h"
9 #include <dt-bindings/clock/mt8195-clk.h>
10 #include <linux/clk-provider.h>
25  * No rst or post divider enable in apu pll, so set "rst_bar_mask" and "en_mask"
62 	struct device_node *node = pdev->dev.of_node;  in clk_mt8195_apusys_pll_probe()
67 		return -ENOMEM;  in clk_mt8195_apusys_pll_probe()
91 	struct device_node *node = pdev->dev.of_node;  in clk_mt8195_apusys_pll_remove()
99 	{ .compatible = "mediatek,mt8195-apusys_pll", },
108 		.name = "clk-mt8195-apusys_pll",
114 MODULE_DESCRIPTION("MediaTek MT8195 AI Processing Unit PLL clocks driver");