clk/mediatek/clk-mt8195-apusys_pll.c

18 #define MT8195_PLL_EN_BIT	(0)
19 #define MT8195_PCW_SHIFT	(0)
33 		.en_mask = 0,						\
34 		.flags = 0,						\
35 		.rst_bar_mask = 0,					\
42 		.tuner_reg = 0,						\
43 		.tuner_en_reg = 0,					\
44 		.tuner_en_bit = 0,					\
47 		.pcw_chg_reg = 0,					\
48 		.en_reg = 0,						\
53 	PLL(CLK_APUSYS_PLL_APUPLL, "apusys_pll_apupll", 0x008, 0x014, 0x00c, 0x00c),
54 	PLL(CLK_APUSYS_PLL_NPUPLL, "apusys_pll_npupll", 0x018, 0x024, 0x01c, 0x01c),
55 	PLL(CLK_APUSYS_PLL_APUPLL1, "apusys_pll_apupll1", 0x028, 0x034, 0x02c, 0x02c),
56 	PLL(CLK_APUSYS_PLL_APUPLL2, "apusys_pll_apupll2", 0x038, 0x044, 0x03c, 0x03c),