clk/mediatek/clk-mt8192.c

1 // SPDX-License-Identifier: GPL-2.0-only
4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 #include "clk-gate.h"
14 #include "clk-mtk.h"
15 #include "clk-mux.h"
17 #include <dt-bindings/clock/mt8192-clk.h>
18 #include <dt-bindings/reset/mt8192-resets.h>
543  * spm_sel is the clock of the always-on co-processor.
583 			mfg_pll_parents, 0x050, 0x054, 0x058, 18, 1, -1, -1),
974 		return -ENOMEM;  in clk_mt8192_reg_mfg_mux_notifier()
980 		return -EINVAL;  in clk_mt8192_reg_mfg_mux_notifier()
982 	mfg_mux_nb->ops = top_mtk_muxes[i].ops;  in clk_mt8192_reg_mfg_mux_notifier()
983 	mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */  in clk_mt8192_reg_mfg_mux_notifier()
1016 	{ .compatible = "mediatek,mt8192-infracfg", .data = &infra_desc },
1017 	{ .compatible = "mediatek,mt8192-pericfg", .data = &peri_desc },
1018 	{ .compatible = "mediatek,mt8192-topckgen", .data = &topck_desc },
1025 		.name = "clk-mt8192",
1033 MODULE_DESCRIPTION("MediaTek MT8192 main clocks driver");