Lines Matching +full:0 +full:x250
17 #define REGOFF_REF2USB 0x8
18 #define REGOFF_HDMI_REF 0x40
52 { .div = 0, .freq = MT8173_PLL_FMAX },
61 PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, PLL_AO,
62 21, 0x204, 24, 0x0, 0x204, 0),
63 PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, PLL_AO,
64 21, 0x214, 24, 0x0, 0x214, 0),
65 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21,
66 0x220, 4, 0x0, 0x224, 0),
67 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BAR, 7,
68 0x230, 4, 0x0, 0x234, 14),
69 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0,
70 0x244, 0, mmpll_div_table),
71 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
72 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),
73 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),
74 PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0),
75 PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0, 0, 21, 0x290, 4, 0x0, 0x294, 0),
76 PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
77 PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
78 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
79 PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
103 .dds_mask = GENMASK(21, 0), \
104 .slope0_value = 0x6003c97, \
105 .slope1_value = 0x6003c97, \
108 .fhctlx_en = BIT(0), \
112 .dt_val = 0x0, \
113 .df_val = 0x9, \
121 FH(CLK_APMIXED_ARMCA7PLL, FH_ARMCA7PLL, 0x38),
122 FH(CLK_APMIXED_ARMCA15PLL, FH_ARMCA15PLL, 0x4c),
123 FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60),
124 FH(CLK_APMIXED_MPLL, FH_MPLL, 0x74),
125 FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x88),
126 FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x9c),
127 FH(CLK_APMIXED_VENCPLL, FH_VENCPLL, 0xb0),
128 FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0xc4),
129 FH(CLK_APMIXED_VCODECPLL, FH_VCODECPLL, 0xd8),
130 FH(CLK_APMIXED_LVDSPLL, FH_LVDSPLL, 0xec),
131 FH(CLK_APMIXED_MSDCPLL2, FH_MSDC2PLL, 0x100),
149 base = of_iomap(node, 0); in clk_mt8173_apmixed_probe()
173 hw = devm_clk_hw_register_divider(&pdev->dev, "hdmi_ref", "tvdpll_594m", 0, in clk_mt8173_apmixed_probe()
182 return 0; in clk_mt8173_apmixed_probe()