clk/mediatek/clk-mt8167.c

24 	FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
525 		0x000, 0, 1),
527 		0x000, 1, 1),
529 		0x000, 2, 1),
531 		0x000, 4, 4),
533 		0x000, 8, 3),
535 		0x000, 11, 3),
537 		0x000, 15, 3),
539 		0x000, 18, 1),
541 		0x000, 19, 1),
543 		0x000, 20, 3),
545 		0x000, 23, 1),
547 		0x000, 24, 2),
549 		0x000, 26, 1),
551 		0x000, 27, 3),
554 		0x004, 0, 7),
556 		0x004, 7, 1),
558 		0x004, 8, 6),
560 		0x004, 15, 1),
562 		0x004, 16, 4),
564 		0x004, 20, 3),
566 		0x004, 23, 3),
569 		0x040, 0, 3),
571 		0x040, 3, 3),
573 		0x040, 6, 3),
575 		0x040, 9, 3),
577 		0x040, 12, 3),
579 		0x040, 15, 3),
581 		0x040, 18, 2),
583 		0x040, 20, 2),
585 		0x040, 22, 1),
587 		0x040, 23, 1),
589 		0x040, 24, 2),
591 		0x040, 26, 2),
593 		0x040, 28, 2),
596 		0x044, 12, 1),
598 		0x044, 13, 1),
600 		0x044, 14, 1),
602 		0x044, 15, 1),
604 		0x044, 16, 1),
606 		0x044, 17, 1),
608 		0x044, 18, 1),
611 		0x07c, 0, 1),
613 		0x07c, 1, 2),
615 		0x07c, 3, 1),
617 		0x07c, 4, 1),
619 		0x07c, 5, 2),
621 		0x07c, 7, 3),
623 		0x07c, 10, 3),
625 		0x07c, 13, 3),
646 	MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000,
648 	MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080,
649 		0, 1),
650 	MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080,
652 	MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080,
654 	MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080,
669 		0x0048, 0, 8),
671 		0x0048, 8, 8),
673 		0x0048, 16, 8),
675 		0x0048, 24, 8),
677 		0x004c, 0, 8),
679 		0x004c, 8, 8),
681 		0x004c, 16, 8),
683 		0x004c, 24, 8),
685 		0x0078, 0, 8),
689 	.set_ofs = 0x50,
690 	.clr_ofs = 0x80,
691 	.sta_ofs = 0x20,
695 	.set_ofs = 0x54,
696 	.clr_ofs = 0x84,
697 	.sta_ofs = 0x24,
701 	.set_ofs = 0x6c,
702 	.clr_ofs = 0x9c,
703 	.sta_ofs = 0x3c,
707 	.set_ofs = 0xa0,
708 	.clr_ofs = 0xb0,
709 	.sta_ofs = 0x70,
713 	.set_ofs = 0xa4,
714 	.clr_ofs = 0xb4,
715 	.sta_ofs = 0x74,
719 	.set_ofs = 0x44,
720 	.clr_ofs = 0x44,
721 	.sta_ofs = 0x44,
750 	GATE_TOP0(CLK_TOP_PWM_MM, "pwm_mm", "pwm_mm_sel", 0),
789 	GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
822 	GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0),
850 	GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),