Lines Matching +full:jz4780 +full:- +full:rtc
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Ingenic JZ4780 SoC CGU driver
5 * Copyright (c) 2013-2015 Imagination Technologies
10 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
111 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_recalc_rate()
170 return -EINVAL; in jz4780_otg_phy_set_rate()
173 spin_lock_irqsave(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
175 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
178 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
180 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
186 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4780_otg_phy_enable()
187 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in jz4780_otg_phy_enable()
196 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4780_otg_phy_disable()
197 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in jz4780_otg_phy_disable()
205 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4780_otg_phy_is_enabled()
206 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in jz4780_otg_phy_is_enabled()
226 struct ingenic_cgu *cgu = ingenic_clk->cgu; in jz4780_core1_enable()
232 spin_lock_irqsave(&cgu->lock, flags); in jz4780_core1_enable()
234 lcr = readl(cgu->base + CGU_REG_LCR); in jz4780_core1_enable()
236 writel(lcr, cgu->base + CGU_REG_LCR); in jz4780_core1_enable()
238 clkgr1 = readl(cgu->base + CGU_REG_CLKGR1); in jz4780_core1_enable()
240 writel(clkgr1, cgu->base + CGU_REG_CLKGR1); in jz4780_core1_enable()
242 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_core1_enable()
245 retval = readl_poll_timeout(cgu->base + CGU_REG_LCR, lcr, in jz4780_core1_enable()
247 if (retval == -ETIMEDOUT) { in jz4780_core1_enable()
269 [JZ4780_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
294 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
300 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
306 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
312 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
318 /* Custom (SoC-specific) OTG PHY */
322 .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 },
330 .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK,
337 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
349 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
350 .div = { CGU_REG_CLOCKCONTROL, 0, 1, 4, 22, -1, -1 },
360 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
361 .div = { CGU_REG_CLOCKCONTROL, 4, 1, 4, -1, -1, -1 },
366 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
369 .div = { CGU_REG_CLOCKCONTROL, 8, 1, 4, 21, -1, -1 },
374 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
381 .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },
382 .div = { CGU_REG_CLOCKCONTROL, 12, 1, 4, 20, -1, -1 },
387 .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },
388 .div = { CGU_REG_CLOCKCONTROL, 16, 1, 4, 20, -1, -1 },
398 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
406 JZ4780_CLK_EPLL, -1 },
414 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 },
421 .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL, -1, -1 },
428 JZ4780_CLK_VPLL, -1 },
436 JZ4780_CLK_VPLL, -1 },
443 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
449 .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
456 .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
463 .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
479 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },
486 .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL, -1, -1 },
492 .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },
507 .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL, -1, -1 },
514 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
524 JZ4780_CLK_VPLL, -1 },
532 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
551 /* Gate-only clocks */
555 .parents = { JZ4780_CLK_AHB2, -1, -1, -1 },
561 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
567 .parents = { JZ4780_CLK_SSI, -1, -1, -1 },
573 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
579 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
585 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
591 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
597 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
603 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
609 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
615 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
621 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
627 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
633 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
639 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
645 .parents = { JZ4780_CLK_SSI, -1, -1, -1 },
651 .parents = { JZ4780_CLK_SSI, -1, -1, -1 },
657 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
663 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
669 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
675 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
681 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
687 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
693 .parents = { JZ4780_CLK_LCD, -1, -1, -1 },
699 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
705 .parents = { JZ4780_CLK_DDR, -1, -1, -1 },
711 .parents = { JZ4780_CLK_DDR, -1, -1, -1 },
717 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
723 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
729 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
735 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
741 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
747 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
753 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
759 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
765 .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
771 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
777 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
783 .parents = { JZ4780_CLK_CPU, -1, -1, -1 },
808 CLK_OF_DECLARE_DRIVER(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init);