clk/ingenic/jz4760-cgu.c

1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/ingenic,jz4760-cgu.h>
45 	0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
61 	unsigned int m, n, od, m_max = (1 << pll_info->m_bits) - 1;  in jz4760_cgu_calc_m_n_od()
67 	n = clamp_val(n, 2, 1 << pll_info->n_bits);  in jz4760_cgu_calc_m_n_od()
72 	for (m = m_max; m >= m_max && n >= 2; n--) {  in jz4760_cgu_calc_m_n_od()
133 			.bypass_bit = -1,
150 		.div = {
151 			CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
158 		.div = {
159 			CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
166 		.div = {
167 			CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1, 0,
174 		.div = {
175 			CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
180 		"mclk", CGU_CLK_DIV,
182 		 * Disabling MCLK or its parents will render DRAM
187 		.div = {
188 			CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
195 		.div = {
196 			CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
206 		.div = {
207 			CGU_REG_CPCCR, 21, 1, 1, 22, -1, -1, 0,
218 		.div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
225 		.div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 },
232 		.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
250 		.div = { CGU_REG_GPSCDR, 0, 1, 4, -1, -1, -1 },
258 		.parents = { JZ4760_CLK_EXT, -1,
261 		.div = { CGU_REG_PCMCDR, 0, 1, 9, -1, -1, -1, BIT(0) },
266 		.parents = { JZ4760_CLK_EXT, -1,
269 		.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1, BIT(0) },
273 		.parents = { JZ4760_CLK_EXT, -1,
276 		.div = { CGU_REG_USBCDR, 0, 1, 8, -1, -1, -1 },
285 		.div = { CGU_REG_MSCCDR, 0, 1, 6, -1, -1, -1, BIT(0) },
291 		.div = { CGU_REG_SSICDR, 0, 1, 6, -1, -1, -1, BIT(0) },
298 		.div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 },
302 	/* Gate-only clocks */
443 CLK_OF_DECLARE_DRIVER(jz4760_cgu, "ingenic,jz4760-cgu", jz4760_cgu_init);
446 CLK_OF_DECLARE_DRIVER(jz4760b_cgu, "ingenic,jz4760b-cgu", jz4760_cgu_init);