clk/ingenic/jz4725b-cgu.c

1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
36 	0x0, 0x1, -1, 0x3,
40 	1, 2, 3, 4, 6, 8,
44 	2, 1,
56 		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
59 			.rate_multiplier = 1,
81 		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
83 			CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
95 		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
97 			CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
104 		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
106 			CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
113 		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
115 			CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
127 		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
129 			CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
136 		.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
138 			CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
146 		.parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
147 		.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
153 		.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
154 		.mux = { CGU_REG_CPCCR, 31, 1 },
155 		.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
160 		.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL, -1, -1 },
161 		.mux = { CGU_REG_SSICDR, 31, 1 },
162 		.div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
168 		.parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
169 		.div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
174 		.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
175 		.mux = { CGU_REG_CPCCR, 29, 1 },
176 		.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
179 	/* Gate-only clocks */
183 		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
189 		.parents = { JZ4725B_CLK_PCLK, -1, -1, -1 },
195 		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
201 		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
207 		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
213 		.parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
219 		.parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
225 		.parents = { JZ4725B_CLK_MCLK/* not sure */, -1, -1, -1 },
231 		.parents = { JZ4725B_CLK_EXT/* not sure */, -1, -1, -1 },
232 		.gate = { CGU_REG_CLKGR, 1 },
245 		.parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 },
246 		.mux = { CGU_REG_OPCR, 2, 1},
251 		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
273 CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);