95 struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base,
97 struct clk_hw *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name,
104 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \  argument
105 	to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
107 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \  argument
109 	to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
112 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \  argument
113 	to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
115 #define imx_clk_pfd(name, parent_name, reg, idx) \  argument
116 	to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
224 #define imx_clk_hw_pll14xx(name, parent_name, base, pll_clk) \  argument
225 	imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk)
228 				const char *parent_name, void __iomem *base,
237 struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
261 		const char *parent_name, void __iomem *base, u32 div_mask);
281 		const char *parent_name, void __iomem *base);
284 		const char *parent_name, unsigned long flags,
303 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
307 	 const char *parent_name, void __iomem *reg, u8 idx);
309 struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
401 struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
477 struct clk_hw *imx93_clk_gate(struct device *dev, const char *name, const char *parent_name,
481 struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,