22 #define PLL_CFG0		0x0  macro
102 	val = readl_relaxed(pll->base + PLL_CFG0);  in clk_sscg_pll_wait_lock()
300 	u32 val = readl_relaxed(pll->base + PLL_CFG0);  in clk_sscg_pll_is_prepared()
310 	val = readl_relaxed(pll->base + PLL_CFG0);  in clk_sscg_pll_prepare()
312 	writel_relaxed(val, pll->base + PLL_CFG0);  in clk_sscg_pll_prepare()
322 	val = readl_relaxed(pll->base + PLL_CFG0);  in clk_sscg_pll_unprepare()
324 	writel_relaxed(val, pll->base + PLL_CFG0);  in clk_sscg_pll_unprepare()
343 	val = readl(pll->base + PLL_CFG0);  in clk_sscg_pll_recalc_rate()
366 	val = readl(pll->base + PLL_CFG0);  in clk_sscg_pll_set_rate()
369 	writel(val, pll->base + PLL_CFG0);  in clk_sscg_pll_set_rate()
390 	val = readl(pll->base + PLL_CFG0);  in clk_sscg_pll_get_parent()
403 	val = readl(pll->base + PLL_CFG0);  in clk_sscg_pll_set_parent()
406 	writel(val, pll->base + PLL_CFG0);  in clk_sscg_pll_set_parent()