33  * struct clk_pllv3 - IMX PLL clock version 3
35  * @base:	 base address of PLL registers
36  * @power_bit:	 pll power bit mask
37  * @powerup_set: set power_bit to power up the PLL
44  * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
61 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)  in clk_pllv3_wait_lock()  argument
63 	u32 val = readl_relaxed(pll->base) & pll->power_bit;  in clk_pllv3_wait_lock()
65 	/* No need to wait for lock when pll is not powered up */  in clk_pllv3_wait_lock()
66 	if ((pll->powerup_set && !val) || (!pll->powerup_set && val))  in clk_pllv3_wait_lock()
69 	return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK,  in clk_pllv3_wait_lock()
75 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_prepare()  local
78 	val = readl_relaxed(pll->base);  in clk_pllv3_prepare()
79 	if (pll->powerup_set)  in clk_pllv3_prepare()
80 		val |= pll->power_bit;  in clk_pllv3_prepare()
82 		val &= ~pll->power_bit;  in clk_pllv3_prepare()
83 	writel_relaxed(val, pll->base);  in clk_pllv3_prepare()
85 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_prepare()
90 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_unprepare()  local
93 	val = readl_relaxed(pll->base);  in clk_pllv3_unprepare()
94 	if (pll->powerup_set)  in clk_pllv3_unprepare()
95 		val &= ~pll->power_bit;  in clk_pllv3_unprepare()
97 		val |= pll->power_bit;  in clk_pllv3_unprepare()
98 	writel_relaxed(val, pll->base);  in clk_pllv3_unprepare()
103 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_is_prepared()  local
105 	if (readl_relaxed(pll->base) & BM_PLL_LOCK)  in clk_pllv3_is_prepared()
114 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_recalc_rate()  local
115 	u32 div = (readl_relaxed(pll->base) >> pll->div_shift)  & pll->div_mask;  in clk_pllv3_recalc_rate()
132 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_set_rate()  local
142 	val = readl_relaxed(pll->base);  in clk_pllv3_set_rate()
143 	val &= ~(pll->div_mask << pll->div_shift);  in clk_pllv3_set_rate()
144 	val |= (div << pll->div_shift);  in clk_pllv3_set_rate()
145 	writel_relaxed(val, pll->base);  in clk_pllv3_set_rate()
147 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_set_rate()
162 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_sys_recalc_rate()  local
163 	u32 div = readl_relaxed(pll->base) & pll->div_mask;  in clk_pllv3_sys_recalc_rate()
188 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_sys_set_rate()  local
197 	val = readl_relaxed(pll->base);  in clk_pllv3_sys_set_rate()
198 	val &= ~pll->div_mask;  in clk_pllv3_sys_set_rate()
200 	writel_relaxed(val, pll->base);  in clk_pllv3_sys_set_rate()
202 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_sys_set_rate()
217 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_av_recalc_rate()  local
218 	u32 mfn = readl_relaxed(pll->base + pll->num_offset);  in clk_pllv3_av_recalc_rate()
219 	u32 mfd = readl_relaxed(pll->base + pll->denom_offset);  in clk_pllv3_av_recalc_rate()
220 	u32 div = readl_relaxed(pll->base) & pll->div_mask;  in clk_pllv3_av_recalc_rate()
264 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_av_set_rate()  local
284 	val = readl_relaxed(pll->base);  in clk_pllv3_av_set_rate()
285 	val &= ~pll->div_mask;  in clk_pllv3_av_set_rate()
287 	writel_relaxed(val, pll->base);  in clk_pllv3_av_set_rate()
288 	writel_relaxed(mfn, pll->base + pll->num_offset);  in clk_pllv3_av_set_rate()
289 	writel_relaxed(mfd, pll->base + pll->denom_offset);  in clk_pllv3_av_set_rate()
291 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_av_set_rate()
348 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_vf610_recalc_rate()  local
351 	mf.mfn = readl_relaxed(pll->base + pll->num_offset);  in clk_pllv3_vf610_recalc_rate()
352 	mf.mfd = readl_relaxed(pll->base + pll->denom_offset);  in clk_pllv3_vf610_recalc_rate()
353 	mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;  in clk_pllv3_vf610_recalc_rate()
369 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_vf610_set_rate()  local
374 	val = readl_relaxed(pll->base);  in clk_pllv3_vf610_set_rate()
376 		val &= ~pll->div_mask;	/* clear bit for mfi=20 */  in clk_pllv3_vf610_set_rate()
378 		val |= pll->div_mask;	/* set bit for mfi=22 */  in clk_pllv3_vf610_set_rate()
379 	writel_relaxed(val, pll->base);  in clk_pllv3_vf610_set_rate()
381 	writel_relaxed(mf.mfn, pll->base + pll->num_offset);  in clk_pllv3_vf610_set_rate()
382 	writel_relaxed(mf.mfd, pll->base + pll->denom_offset);  in clk_pllv3_vf610_set_rate()
384 	return clk_pllv3_wait_lock(pll);  in clk_pllv3_vf610_set_rate()
399 	struct clk_pllv3 *pll = to_clk_pllv3(hw);  in clk_pllv3_enet_recalc_rate()  local
401 	return pll->ref_clock;  in clk_pllv3_enet_recalc_rate()
415 	struct clk_pllv3 *pll;  in imx_clk_hw_pllv3()  local
421 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in imx_clk_hw_pllv3()
422 	if (!pll)  in imx_clk_hw_pllv3()
425 	pll->power_bit = BM_PLL_POWER;  in imx_clk_hw_pllv3()
426 	pll->num_offset = PLL_NUM_OFFSET;  in imx_clk_hw_pllv3()
427 	pll->denom_offset = PLL_DENOM_OFFSET;  in imx_clk_hw_pllv3()
435 		pll->num_offset = PLL_VF610_NUM_OFFSET;  in imx_clk_hw_pllv3()
436 		pll->denom_offset = PLL_VF610_DENOM_OFFSET;  in imx_clk_hw_pllv3()
439 		pll->div_shift = 1;  in imx_clk_hw_pllv3()
443 		pll->powerup_set = true;  in imx_clk_hw_pllv3()
446 		pll->num_offset = PLL_IMX7_NUM_OFFSET;  in imx_clk_hw_pllv3()
447 		pll->denom_offset = PLL_IMX7_DENOM_OFFSET;  in imx_clk_hw_pllv3()
453 		pll->power_bit = IMX7_ENET_PLL_POWER;  in imx_clk_hw_pllv3()
454 		pll->ref_clock = 1000000000;  in imx_clk_hw_pllv3()
458 		pll->ref_clock = 500000000;  in imx_clk_hw_pllv3()
462 		pll->power_bit = IMX7_DDR_PLL_POWER;  in imx_clk_hw_pllv3()
463 		pll->num_offset = PLL_IMX7_NUM_OFFSET;  in imx_clk_hw_pllv3()
464 		pll->denom_offset = PLL_IMX7_DENOM_OFFSET;  in imx_clk_hw_pllv3()
470 	pll->base = base;  in imx_clk_hw_pllv3()
471 	pll->div_mask = div_mask;  in imx_clk_hw_pllv3()
479 	pll->hw.init = &init;  in imx_clk_hw_pllv3()
480 	hw = &pll->hw;  in imx_clk_hw_pllv3()
484 		kfree(pll);  in imx_clk_hw_pllv3()