84 	struct pcc_reset_dev *pcc_reset = to_pcc_reset_dev(rcdev);  in imx8ulp_pcc_assert()  local
85 	u32 offset = pcc_reset->resets[id];  in imx8ulp_pcc_assert()
89 	spin_lock_irqsave(pcc_reset->lock, flags);  in imx8ulp_pcc_assert()
91 	val = readl(pcc_reset->base + offset);  in imx8ulp_pcc_assert()
93 	writel(val, pcc_reset->base + offset);  in imx8ulp_pcc_assert()
95 	spin_unlock_irqrestore(pcc_reset->lock, flags);  in imx8ulp_pcc_assert()
102 	struct pcc_reset_dev *pcc_reset = to_pcc_reset_dev(rcdev);  in imx8ulp_pcc_deassert()  local
103 	u32 offset = pcc_reset->resets[id];  in imx8ulp_pcc_deassert()
107 	spin_lock_irqsave(pcc_reset->lock, flags);  in imx8ulp_pcc_deassert()
109 	val = readl(pcc_reset->base + offset);  in imx8ulp_pcc_deassert()
111 	writel(val, pcc_reset->base + offset);  in imx8ulp_pcc_deassert()
113 	spin_unlock_irqrestore(pcc_reset->lock, flags);  in imx8ulp_pcc_deassert()
128 	struct pcc_reset_dev *pcc_reset;  in imx8ulp_pcc_reset_init()  local
130 	pcc_reset = devm_kzalloc(dev, sizeof(*pcc_reset), GFP_KERNEL);  in imx8ulp_pcc_reset_init()
131 	if (!pcc_reset)  in imx8ulp_pcc_reset_init()
134 	pcc_reset->base = base;  in imx8ulp_pcc_reset_init()
135 	pcc_reset->lock = &imx_ccm_lock;  in imx8ulp_pcc_reset_init()
136 	pcc_reset->resets = resets;  in imx8ulp_pcc_reset_init()
137 	pcc_reset->rcdev.owner = THIS_MODULE;  in imx8ulp_pcc_reset_init()
138 	pcc_reset->rcdev.nr_resets = nr_resets;  in imx8ulp_pcc_reset_init()
139 	pcc_reset->rcdev.ops = &imx8ulp_pcc_reset_ops;  in imx8ulp_pcc_reset_init()
140 	pcc_reset->rcdev.of_node = np;  in imx8ulp_pcc_reset_init()
142 	return devm_reset_controller_register(dev, &pcc_reset->rcdev);  in imx8ulp_pcc_reset_init()