1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx8ulp-clock.h>
12 #include <linux/reset-controller.h>
85 	u32 offset = pcc_reset->resets[id];  in imx8ulp_pcc_assert()
89 	spin_lock_irqsave(pcc_reset->lock, flags);  in imx8ulp_pcc_assert()
91 	val = readl(pcc_reset->base + offset);  in imx8ulp_pcc_assert()
93 	writel(val, pcc_reset->base + offset);  in imx8ulp_pcc_assert()
95 	spin_unlock_irqrestore(pcc_reset->lock, flags);  in imx8ulp_pcc_assert()
103 	u32 offset = pcc_reset->resets[id];  in imx8ulp_pcc_deassert()
107 	spin_lock_irqsave(pcc_reset->lock, flags);  in imx8ulp_pcc_deassert()
109 	val = readl(pcc_reset->base + offset);  in imx8ulp_pcc_deassert()
111 	writel(val, pcc_reset->base + offset);  in imx8ulp_pcc_deassert()
113 	spin_unlock_irqrestore(pcc_reset->lock, flags);  in imx8ulp_pcc_deassert()
126 	struct device_node *np = pdev->dev.of_node;  in imx8ulp_pcc_reset_init()
127 	struct device *dev = &pdev->dev;  in imx8ulp_pcc_reset_init()
132 		return -ENOMEM;  in imx8ulp_pcc_reset_init()
134 	pcc_reset->base = base;  in imx8ulp_pcc_reset_init()
135 	pcc_reset->lock = &imx_ccm_lock;  in imx8ulp_pcc_reset_init()
136 	pcc_reset->resets = resets;  in imx8ulp_pcc_reset_init()
137 	pcc_reset->rcdev.owner = THIS_MODULE;  in imx8ulp_pcc_reset_init()
138 	pcc_reset->rcdev.nr_resets = nr_resets;  in imx8ulp_pcc_reset_init()
139 	pcc_reset->rcdev.ops = &imx8ulp_pcc_reset_ops;  in imx8ulp_pcc_reset_init()
140 	pcc_reset->rcdev.of_node = np;  in imx8ulp_pcc_reset_init()
142 	return devm_reset_controller_register(dev, &pcc_reset->rcdev);  in imx8ulp_pcc_reset_init()
147 	struct device *dev = &pdev->dev;  in imx8ulp_clk_cgc1_init()
155 		return -ENOMEM;  in imx8ulp_clk_cgc1_init()
157 	clk_data->num = IMX8ULP_CLK_CGC1_END;  in imx8ulp_clk_cgc1_init()
158 	clks = clk_data->hws;  in imx8ulp_clk_cgc1_init()
224 	imx_check_clk_hws(clks, clk_data->num);  in imx8ulp_clk_cgc1_init()
231 	struct device *dev = &pdev->dev;  in imx8ulp_clk_cgc2_init()
239 		return -ENOMEM;  in imx8ulp_clk_cgc2_init()
241 	clk_data->num = IMX8ULP_CLK_CGC2_END;  in imx8ulp_clk_cgc2_init()
242 	clks = clk_data->hws;  in imx8ulp_clk_cgc2_init()
306 	imx_check_clk_hws(clks, clk_data->num);  in imx8ulp_clk_cgc2_init()
313 	struct device *dev = &pdev->dev;  in imx8ulp_clk_pcc3_init()
322 		return -ENOMEM;  in imx8ulp_clk_pcc3_init()
324 	clk_data->num = IMX8ULP_CLK_PCC3_END;  in imx8ulp_clk_pcc3_init()
325 	clks = clk_data->hws;  in imx8ulp_clk_pcc3_init()
327 	/* PCC3 */  in imx8ulp_clk_pcc3_init()
382 	imx_check_clk_hws(clks, clk_data->num);  in imx8ulp_clk_pcc3_init()
390 	/* register the pcc3 reset controller */  in imx8ulp_clk_pcc3_init()
396 	struct device *dev = &pdev->dev;  in imx8ulp_clk_pcc4_init()
405 		return -ENOMEM;  in imx8ulp_clk_pcc4_init()
407 	clk_data->num = IMX8ULP_CLK_PCC4_END;  in imx8ulp_clk_pcc4_init()
408 	clks = clk_data->hws;  in imx8ulp_clk_pcc4_init()
438 	imx_check_clk_hws(clks, clk_data->num);  in imx8ulp_clk_pcc4_init()
451 	struct device *dev = &pdev->dev;  in imx8ulp_clk_pcc5_init()
460 		return -ENOMEM;  in imx8ulp_clk_pcc5_init()
462 	clk_data->num = IMX8ULP_CLK_PCC5_END;  in imx8ulp_clk_pcc5_init()
463 	clks = clk_data->hws;  in imx8ulp_clk_pcc5_init()
526 	imx_check_clk_hws(clks, clk_data->num);  in imx8ulp_clk_pcc5_init()
540 	probe = of_device_get_match_data(&pdev->dev);  in imx8ulp_clk_probe()
549 	{ .compatible = "fsl,imx8ulp-pcc3", .data = imx8ulp_clk_pcc3_init },
550 	{ .compatible = "fsl,imx8ulp-pcc4", .data = imx8ulp_clk_pcc4_init },
551 	{ .compatible = "fsl,imx8ulp-pcc5", .data = imx8ulp_clk_pcc5_init },
552 	{ .compatible = "fsl,imx8ulp-cgc2", .data = imx8ulp_clk_cgc2_init },
553 	{ .compatible = "fsl,imx8ulp-cgc1", .data = imx8ulp_clk_cgc1_init },