clk/imx/clk-imx7d.c

44 static const char *arm_a7_sel[] = { "osc", "pll_arm_main_clk",
49 static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk",
54 static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
58 static const char *disp_axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
62 static const char *enet_axi_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
67 static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
72 static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
83 static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk",
88 static const char *dram_alt_sel[] = { "osc", "pll_dram_533m_clk",
93 static const char *usb_hsic_sel[] = { "osc", "pll_sys_main_clk",
97 static const char *pcie_ctrl_sel[] = { "osc", "pll_enet_250m_clk",
102 static const char *pcie_phy_sel[] = { "osc", "pll_enet_100m_clk",
106 static const char *epdc_pixel_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
110 static const char *lcdif_pixel_sel[] = { "osc", "pll_sys_pfd5_clk",
115 static const char *mipi_dsi_sel[] = { "osc", "pll_sys_pfd5_clk",
119 static const char *mipi_csi_sel[] = { "osc", "pll_sys_pfd4_clk",
123 static const char *mipi_dphy_sel[] = { "osc", "pll_sys_main_120m_clk",
127 static const char *sai1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
131 static const char *sai2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
135 static const char *sai3_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
139 static const char *spdif_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
143 static const char *enet1_ref_sel[] = { "osc", "pll_enet_125m_clk",
148 static const char *enet1_time_sel[] = { "osc", "pll_enet_100m_clk",
152 static const char *enet2_ref_sel[] = { "osc", "pll_enet_125m_clk",
157 static const char *enet2_time_sel[] = { "osc", "pll_enet_100m_clk",
161 static const char *enet_phy_ref_sel[] = { "osc", "pll_enet_25m_clk",
166 static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
171 static const char *nand_sel[] = { "osc", "pll_sys_main_clk",
176 static const char *qspi_sel[] = { "osc", "pll_sys_pfd4_clk",
180 static const char *usdhc1_sel[] = { "osc", "pll_sys_pfd0_392m_clk",
184 static const char *usdhc2_sel[] = { "osc", "pll_sys_pfd0_392m_clk",
188 static const char *usdhc3_sel[] = { "osc", "pll_sys_pfd0_392m_clk",
192 static const char *can1_sel[] = { "osc", "pll_sys_main_120m_clk",
197 static const char *can2_sel[] = { "osc", "pll_sys_main_120m_clk",
202 static const char *i2c1_sel[] = { "osc", "pll_sys_main_120m_clk",
207 static const char *i2c2_sel[] = { "osc", "pll_sys_main_120m_clk",
212 static const char *i2c3_sel[] = { "osc", "pll_sys_main_120m_clk",
217 static const char *i2c4_sel[] = { "osc", "pll_sys_main_120m_clk",
222 static const char *uart1_sel[] = { "osc", "pll_sys_main_240m_clk",
227 static const char *uart2_sel[] = { "osc", "pll_sys_main_240m_clk",
232 static const char *uart3_sel[] = { "osc", "pll_sys_main_240m_clk",
237 static const char *uart4_sel[] = { "osc", "pll_sys_main_240m_clk",
242 static const char *uart5_sel[] = { "osc", "pll_sys_main_240m_clk",
247 static const char *uart6_sel[] = { "osc", "pll_sys_main_240m_clk",
252 static const char *uart7_sel[] = { "osc", "pll_sys_main_240m_clk",
257 static const char *ecspi1_sel[] = { "osc", "pll_sys_main_240m_clk",
262 static const char *ecspi2_sel[] = { "osc", "pll_sys_main_240m_clk",
267 static const char *ecspi3_sel[] = { "osc", "pll_sys_main_240m_clk",
272 static const char *ecspi4_sel[] = { "osc", "pll_sys_main_240m_clk",
277 static const char *pwm1_sel[] = { "osc", "pll_enet_100m_clk",
281 static const char *pwm2_sel[] = { "osc", "pll_enet_100m_clk",
285 static const char *pwm3_sel[] = { "osc", "pll_enet_100m_clk",
289 static const char *pwm4_sel[] = { "osc", "pll_enet_100m_clk",
293 static const char *flextimer1_sel[] = { "osc", "pll_enet_100m_clk",
297 static const char *flextimer2_sel[] = { "osc", "pll_enet_100m_clk",
301 static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
306 static const char *sim2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
311 static const char *gpt1_sel[] = { "osc", "pll_enet_100m_clk",
315 static const char *gpt2_sel[] = { "osc", "pll_enet_100m_clk",
319 static const char *gpt3_sel[] = { "osc", "pll_enet_100m_clk",
323 static const char *gpt4_sel[] = { "osc", "pll_enet_100m_clk",
327 static const char *trace_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
332 static const char *wdog_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
337 static const char *csi_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
342 static const char *audio_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
347 static const char *wrclk_sel[] = { "osc", "pll_enet_40m_clk",
352 static const char *clko1_sel[] = { "osc", "pll_sys_main_clk",
356 static const char *clko2_sel[] = { "osc", "pll_sys_main_240m_clk",
369 static const char *pll_bypass_src_sel[] = { "osc", "dummy", };
394 	hws[IMX7D_OSC_24M_CLK] = imx_get_clk_hw_by_name(ccm_node, "osc");  in imx7d_clocks_init()
409 …hws[IMX7D_PLL_ARM_MAIN]  = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "osc", base + 0x60, 0x7…  in imx7d_clocks_init()
410 …hws[IMX7D_PLL_DRAM_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_DDR_IMX7, "pll_dram_main", "osc", base + 0x7…  in imx7d_clocks_init()
411 …hws[IMX7D_PLL_SYS_MAIN]  = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll_sys_main", "osc", base + 0xb0,…  in imx7d_clocks_init()
412 …hws[IMX7D_PLL_ENET_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_ENET_IMX7, "pll_enet_main", "osc", base + 0x…  in imx7d_clocks_init()
413 …hws[IMX7D_PLL_AUDIO_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_AV_IMX7, "pll_audio_main", "osc", base + 0x…  in imx7d_clocks_init()
414 …hws[IMX7D_PLL_VIDEO_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_AV_IMX7, "pll_video_main", "osc", base + 0x…  in imx7d_clocks_init()
857 	hws[IMX7D_GPT_3M_CLK] = imx_clk_hw_fixed_factor("gpt_3m", "osc", 1, 8);  in imx7d_clocks_init()
882 	hws[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb1_main_clk", "osc", 20, 1);  in imx7d_clocks_init()
883 	hws[IMX7D_USB_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb_main_clk", "osc", 20, 1);  in imx7d_clocks_init()