1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright 2013-2014 Freescale Semiconductor, Inc.
14 #include <dt-bindings/clock/imx6sl-clock.h>
34 static const char *step_sels[]		= { "osc", "pll2_pfd2", };
39 static const char *periph_clk2_sels[]	= { "pll3_usb_otg", "osc", "osc", "dummy", };
43 static const char *csi_sels[]		= { "osc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
47 static const char *perclk_sels[]	= { "ipg", "osc", };
55 static const char *ecspi_sels[]		= { "pll3_60m", "osc", };
56 static const char *uart_sels[]		= { "pll3_80m", "osc", };
60 	"pll3_pfd2", "pll3_pfd3", "osc", "dummy", "dummy", "dummy", "dummy", "dummy",
63 static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", };
123  * 396MHz   ->   132MHz;
124  * 792MHz   ->   158.4MHz;
125  * 996MHz   ->   142.3MHz;
193 	clk_hw_data->num = IMX6SL_CLK_END;  in imx6sl_clocks_init()
194 	hws = clk_hw_data->hws;  in imx6sl_clocks_init()
198 	hws[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock_hw("osc", 0);  in imx6sl_clocks_init()
202 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");  in imx6sl_clocks_init()
217 	hws[IMX6SL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS,     "pll1", "osc", base + 0x00, 0x7f);  in imx6sl_clocks_init()
218 	hws[IMX6SL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);  in imx6sl_clocks_init()
219 	hws[IMX6SL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB,     "pll3", "osc", base + 0x10, 0x3);  in imx6sl_clocks_init()
220 	hws[IMX6SL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV,      "pll4", "osc", base + 0x70, 0x7f);  in imx6sl_clocks_init()
221 	hws[IMX6SL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV,      "pll5", "osc", base + 0xa0, 0x7f);  in imx6sl_clocks_init()
222 	hws[IMX6SL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET,    "pll6", "osc", base + 0xe0, 0x3);  in imx6sl_clocks_init()
223 	hws[IMX6SL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB,     "pll7", "osc", base + 0x20, 0x3);  in imx6sl_clocks_init()
233 	/* Do not bypass PLLs initially */  in imx6sl_clocks_init()
234 	clk_set_parent(hws[IMX6SL_PLL1_BYPASS]->clk, hws[IMX6SL_CLK_PLL1]->clk);  in imx6sl_clocks_init()
235 	clk_set_parent(hws[IMX6SL_PLL2_BYPASS]->clk, hws[IMX6SL_CLK_PLL2]->clk);  in imx6sl_clocks_init()
236 	clk_set_parent(hws[IMX6SL_PLL3_BYPASS]->clk, hws[IMX6SL_CLK_PLL3]->clk);  in imx6sl_clocks_init()
237 	clk_set_parent(hws[IMX6SL_PLL4_BYPASS]->clk, hws[IMX6SL_CLK_PLL4]->clk);  in imx6sl_clocks_init()
238 	clk_set_parent(hws[IMX6SL_PLL5_BYPASS]->clk, hws[IMX6SL_CLK_PLL5]->clk);  in imx6sl_clocks_init()
239 	clk_set_parent(hws[IMX6SL_PLL6_BYPASS]->clk, hws[IMX6SL_CLK_PLL6]->clk);  in imx6sl_clocks_init()
240 	clk_set_parent(hws[IMX6SL_PLL7_BYPASS]->clk, hws[IMX6SL_CLK_PLL7]->clk);  in imx6sl_clocks_init()
423 	ret = clk_set_rate(hws[IMX6SL_CLK_AHB]->clk, 132000000);  in imx6sl_clocks_init()
429 		clk_prepare_enable(hws[IMX6SL_CLK_USBPHY1_GATE]->clk);  in imx6sl_clocks_init()
430 		clk_prepare_enable(hws[IMX6SL_CLK_USBPHY2_GATE]->clk);  in imx6sl_clocks_init()
433 	/* Audio-related clocks configuration */  in imx6sl_clocks_init()
434 	clk_set_parent(hws[IMX6SL_CLK_SPDIF0_SEL]->clk, hws[IMX6SL_CLK_PLL3_PFD3]->clk);  in imx6sl_clocks_init()
437 	clk_set_parent(hws[IMX6SL_CLK_LCDIF_PIX_SEL]->clk,  in imx6sl_clocks_init()
438 			hws[IMX6SL_CLK_PLL5_VIDEO_DIV]->clk);  in imx6sl_clocks_init()
440 	clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk,  in imx6sl_clocks_init()
441 		       hws[IMX6SL_CLK_PLL2_PFD2]->clk);  in imx6sl_clocks_init()
445 CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);