clk/imx/clk-imx1.c

17 #define MX1_CCM_BASE_ADDR	0x0021b000
18 #define MX1_TIM1_BASE_ADDR	0x00220000
29 #define CCM_CSCR	(ccm + 0x0000)
30 #define CCM_MPCTL0	(ccm + 0x0004)
31 #define CCM_SPCTL0	(ccm + 0x000c)
32 #define CCM_PCDR	(ccm + 0x0020)
33 #define SCM_GCCR	(ccm + 0x0810)
37 	ccm = of_iomap(np, 0);  in mx1_clocks_init_dt()
40 	clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0);  in mx1_clocks_init_dt()
47 	clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);  in mx1_clocks_init_dt()
54 	clk[IMX1_CLK_PER1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);  in mx1_clocks_init_dt()
64 	clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);  in mx1_clocks_init_dt()