1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
15 	struct clk_divider divider;  member
23 	return container_of(div, struct clk_divider_gate, divider);  in to_clk_divider_gate()
32 	val = readl(div->reg) >> div->shift;  in clk_divider_gate_recalc_rate_ro()
33 	val &= clk_div_mask(div->width);  in clk_divider_gate_recalc_rate_ro()
37 	return divider_recalc_rate(hw, parent_rate, val, div->table,  in clk_divider_gate_recalc_rate_ro()
38 				   div->flags, div->width);  in clk_divider_gate_recalc_rate_ro()
49 	spin_lock_irqsave(div->lock, flags);  in clk_divider_gate_recalc_rate()
52 		val = div_gate->cached_val;  in clk_divider_gate_recalc_rate()
54 		val = readl(div->reg) >> div->shift;  in clk_divider_gate_recalc_rate()
55 		val &= clk_div_mask(div->width);  in clk_divider_gate_recalc_rate()
58 	spin_unlock_irqrestore(div->lock, flags);  in clk_divider_gate_recalc_rate()
63 	return divider_recalc_rate(hw, parent_rate, val, div->table,  in clk_divider_gate_recalc_rate()
64 				   div->flags, div->width);  in clk_divider_gate_recalc_rate()
82 	value = divider_get_val(rate, parent_rate, div->table,  in clk_divider_gate_set_rate()
83 				div->width, div->flags);  in clk_divider_gate_set_rate()
87 	spin_lock_irqsave(div->lock, flags);  in clk_divider_gate_set_rate()
90 		val = readl(div->reg);  in clk_divider_gate_set_rate()
91 		val &= ~(clk_div_mask(div->width) << div->shift);  in clk_divider_gate_set_rate()
92 		val |= (u32)value << div->shift;  in clk_divider_gate_set_rate()
93 		writel(val, div->reg);  in clk_divider_gate_set_rate()
95 		div_gate->cached_val = value;  in clk_divider_gate_set_rate()
98 	spin_unlock_irqrestore(div->lock, flags);  in clk_divider_gate_set_rate()
110 	if (!div_gate->cached_val) {  in clk_divider_enable()
111 		pr_err("%s: no valid preset rate\n", clk_hw_get_name(hw));  in clk_divider_enable()
112 		return -EINVAL;  in clk_divider_enable()
115 	spin_lock_irqsave(div->lock, flags);  in clk_divider_enable()
117 	val = readl(div->reg);  in clk_divider_enable()
118 	val |= div_gate->cached_val << div->shift;  in clk_divider_enable()
119 	writel(val, div->reg);  in clk_divider_enable()
121 	spin_unlock_irqrestore(div->lock, flags);  in clk_divider_enable()
133 	spin_lock_irqsave(div->lock, flags);  in clk_divider_disable()
136 	val = readl(div->reg) >> div->shift;  in clk_divider_disable()
137 	val &= clk_div_mask(div->width);  in clk_divider_disable()
138 	div_gate->cached_val = val;  in clk_divider_disable()
139 	writel(0, div->reg);  in clk_divider_disable()
141 	spin_unlock_irqrestore(div->lock, flags);  in clk_divider_disable()
149 	val = readl(div->reg) >> div->shift;  in clk_divider_is_enabled()
150 	val &= clk_div_mask(div->width);  in clk_divider_is_enabled()
170  * NOTE: In order to reuse the most code from the common divider,
171  * we also design our divider following the way that provids an extra
190 		return ERR_PTR(-ENOMEM);  in imx_clk_hw_divider_gate()
201 	div_gate->divider.reg = reg;  in imx_clk_hw_divider_gate()
202 	div_gate->divider.shift = shift;  in imx_clk_hw_divider_gate()
203 	div_gate->divider.width = width;  in imx_clk_hw_divider_gate()
204 	div_gate->divider.lock = lock;  in imx_clk_hw_divider_gate()
205 	div_gate->divider.table = table;  in imx_clk_hw_divider_gate()
206 	div_gate->divider.hw.init = &init;  in imx_clk_hw_divider_gate()
207 	div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags;  in imx_clk_hw_divider_gate()
211 	div_gate->cached_val = val;  in imx_clk_hw_divider_gate()
213 	hw = &div_gate->divider.hw;  in imx_clk_hw_divider_gate()