1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
36 	prediv_value = readl(divider->reg) >> divider->shift;  in imx8m_clk_composite_divider_recalc_rate()
37 	prediv_value &= clk_div_mask(divider->width);  in imx8m_clk_composite_divider_recalc_rate()
40 						NULL, divider->flags,  in imx8m_clk_composite_divider_recalc_rate()
41 						divider->width);  in imx8m_clk_composite_divider_recalc_rate()
43 	div_value = readl(divider->reg) >> PCG_DIV_SHIFT;  in imx8m_clk_composite_divider_recalc_rate()
47 				   divider->flags, PCG_DIV_WIDTH);  in imx8m_clk_composite_divider_recalc_rate()
56 	int ret = -EINVAL;  in imx8m_clk_composite_compute_dividers()
63 			int new_error = ((parent_rate / div1) / div2) - rate;  in imx8m_clk_composite_compute_dividers()
105 		return -EINVAL;  in imx8m_clk_composite_divider_set_rate()
107 	spin_lock_irqsave(divider->lock, flags);  in imx8m_clk_composite_divider_set_rate()
109 	orig = readl(divider->reg);  in imx8m_clk_composite_divider_set_rate()
110 	val = orig & ~((clk_div_mask(divider->width) << divider->shift) |  in imx8m_clk_composite_divider_set_rate()
113 	val |= (u32)(prediv_value  - 1) << divider->shift;  in imx8m_clk_composite_divider_set_rate()
114 	val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;  in imx8m_clk_composite_divider_set_rate()
117 		writel(val, divider->reg);  in imx8m_clk_composite_divider_set_rate()
119 	spin_unlock_irqrestore(divider->lock, flags);  in imx8m_clk_composite_divider_set_rate()
132 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in imx8m_divider_determine_rate()
135 		val = readl(divider->reg);  in imx8m_divider_determine_rate()
136 		prediv_value = val >> divider->shift;  in imx8m_divider_determine_rate()
137 		prediv_value &= clk_div_mask(divider->width);  in imx8m_divider_determine_rate()
144 		return divider_ro_determine_rate(hw, req, divider->table,  in imx8m_divider_determine_rate()
146 						 divider->flags, prediv_value * div_value);  in imx8m_divider_determine_rate()
149 	return divider_determine_rate(hw, req, divider->table,  in imx8m_divider_determine_rate()
151 				      divider->flags);  in imx8m_divider_determine_rate()
168 	struct clk_mux *mux = to_clk_mux(hw);  in imx8m_clk_composite_mux_set_parent()  local
169 	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);  in imx8m_clk_composite_mux_set_parent()
171 	u32 reg;  in imx8m_clk_composite_mux_set_parent()  local
173 	if (mux->lock)  in imx8m_clk_composite_mux_set_parent()
174 		spin_lock_irqsave(mux->lock, flags);  in imx8m_clk_composite_mux_set_parent()
176 	reg = readl(mux->reg);  in imx8m_clk_composite_mux_set_parent()
177 	reg &= ~(mux->mask << mux->shift);  in imx8m_clk_composite_mux_set_parent()
178 	val = val << mux->shift;  in imx8m_clk_composite_mux_set_parent()
179 	reg |= val;  in imx8m_clk_composite_mux_set_parent()
181 	 * write twice to make sure non-target interface  in imx8m_clk_composite_mux_set_parent()
184 	writel(reg, mux->reg);  in imx8m_clk_composite_mux_set_parent()
185 	writel(reg, mux->reg);  in imx8m_clk_composite_mux_set_parent()
187 	if (mux->lock)  in imx8m_clk_composite_mux_set_parent()
188 		spin_unlock_irqrestore(mux->lock, flags);  in imx8m_clk_composite_mux_set_parent()
213 	spin_lock_irqsave(gate->lock, flags);  in imx8m_clk_composite_gate_enable()
215 	val = readl(gate->reg);  in imx8m_clk_composite_gate_enable()
216 	val |= BIT(gate->bit_idx);  in imx8m_clk_composite_gate_enable()
217 	writel(val, gate->reg);  in imx8m_clk_composite_gate_enable()
219 	spin_unlock_irqrestore(gate->lock, flags);  in imx8m_clk_composite_gate_enable()
237 					int num_parents, void __iomem *reg,  in __imx8m_clk_hw_composite()  argument
241 	struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;  in __imx8m_clk_hw_composite()
245 	struct clk_mux *mux;  in __imx8m_clk_hw_composite()  local
250 	mux = kzalloc(sizeof(*mux), GFP_KERNEL);  in __imx8m_clk_hw_composite()
251 	if (!mux)  in __imx8m_clk_hw_composite()
254 	mux_hw = &mux->hw;  in __imx8m_clk_hw_composite()
255 	mux->reg = reg;  in __imx8m_clk_hw_composite()
256 	mux->shift = PCG_PCS_SHIFT;  in __imx8m_clk_hw_composite()
257 	mux->mask = PCG_PCS_MASK;  in __imx8m_clk_hw_composite()
258 	mux->lock = &imx_ccm_lock;  in __imx8m_clk_hw_composite()
264 	div_hw = &div->hw;  in __imx8m_clk_hw_composite()
265 	div->reg = reg;  in __imx8m_clk_hw_composite()
267 		div->shift = PCG_DIV_SHIFT;  in __imx8m_clk_hw_composite()
268 		div->width = PCG_CORE_DIV_WIDTH;  in __imx8m_clk_hw_composite()
272 		div->shift = PCG_PREDIV_SHIFT;  in __imx8m_clk_hw_composite()
273 		div->width = PCG_PREDIV_WIDTH;  in __imx8m_clk_hw_composite()
277 		div->shift = PCG_PREDIV_SHIFT;  in __imx8m_clk_hw_composite()
278 		div->width = PCG_PREDIV_WIDTH;  in __imx8m_clk_hw_composite()
285 	div->lock = &imx_ccm_lock;  in __imx8m_clk_hw_composite()
286 	div->flags = CLK_DIVIDER_ROUND_CLOSEST;  in __imx8m_clk_hw_composite()
293 	gate_hw = &gate->hw;  in __imx8m_clk_hw_composite()
294 	gate->reg = reg;  in __imx8m_clk_hw_composite()
295 	gate->bit_idx = PCG_CGC_SHIFT;  in __imx8m_clk_hw_composite()
296 	gate->lock = &imx_ccm_lock;  in __imx8m_clk_hw_composite()
315 	kfree(mux);  in __imx8m_clk_hw_composite()