Lines Matching +full:reg +full:- +full:init
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2012-2013 Hisilicon Limited.
6 * Copyright (c) 2012-2013 Linaro Limited.
13 #include <linux/clk-provider.h>
36 u32 reg; in clkgate_separated_enable() local
39 if (sclk->lock) in clkgate_separated_enable()
40 spin_lock_irqsave(sclk->lock, flags); in clkgate_separated_enable()
41 reg = BIT(sclk->bit_idx); in clkgate_separated_enable()
42 writel_relaxed(reg, sclk->enable); in clkgate_separated_enable()
43 readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); in clkgate_separated_enable()
44 if (sclk->lock) in clkgate_separated_enable()
45 spin_unlock_irqrestore(sclk->lock, flags); in clkgate_separated_enable()
53 u32 reg; in clkgate_separated_disable() local
56 if (sclk->lock) in clkgate_separated_disable()
57 spin_lock_irqsave(sclk->lock, flags); in clkgate_separated_disable()
58 reg = BIT(sclk->bit_idx); in clkgate_separated_disable()
59 writel_relaxed(reg, sclk->enable + CLKGATE_SEPERATED_DISABLE); in clkgate_separated_disable()
60 readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); in clkgate_separated_disable()
61 if (sclk->lock) in clkgate_separated_disable()
62 spin_unlock_irqrestore(sclk->lock, flags); in clkgate_separated_disable()
68 u32 reg; in clkgate_separated_is_enabled() local
71 reg = readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); in clkgate_separated_is_enabled()
72 reg &= BIT(sclk->bit_idx); in clkgate_separated_is_enabled()
74 return reg ? 1 : 0; in clkgate_separated_is_enabled()
86 void __iomem *reg, u8 bit_idx, in hisi_register_clkgate_sep() argument
91 struct clk_init_data init; in hisi_register_clkgate_sep() local
95 return ERR_PTR(-ENOMEM); in hisi_register_clkgate_sep()
97 init.name = name; in hisi_register_clkgate_sep()
98 init.ops = &clkgate_separated_ops; in hisi_register_clkgate_sep()
99 init.flags = flags; in hisi_register_clkgate_sep()
100 init.parent_names = (parent_name ? &parent_name : NULL); in hisi_register_clkgate_sep()
101 init.num_parents = (parent_name ? 1 : 0); in hisi_register_clkgate_sep()
103 sclk->enable = reg + CLKGATE_SEPERATED_ENABLE; in hisi_register_clkgate_sep()
104 sclk->bit_idx = bit_idx; in hisi_register_clkgate_sep()
105 sclk->flags = clk_gate_flags; in hisi_register_clkgate_sep()
106 sclk->hw.init = &init; in hisi_register_clkgate_sep()
107 sclk->lock = lock; in hisi_register_clkgate_sep()
109 clk = clk_register(dev, &sclk->hw); in hisi_register_clkgate_sep()