Lines Matching +full:0 +full:x01a0
22 #define CRG_BASE_ADDR 0x18020000
62 { HI3559AV100_FIXED_1188M, "1188m", NULL, 0, 1188000000, },
63 { HI3559AV100_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
64 { HI3559AV100_FIXED_842M, "842m", NULL, 0, 842000000, },
65 { HI3559AV100_FIXED_792M, "792m", NULL, 0, 792000000, },
66 { HI3559AV100_FIXED_750M, "750m", NULL, 0, 750000000, },
67 { HI3559AV100_FIXED_710M, "710m", NULL, 0, 710000000, },
68 { HI3559AV100_FIXED_680M, "680m", NULL, 0, 680000000, },
69 { HI3559AV100_FIXED_667M, "667m", NULL, 0, 667000000, },
70 { HI3559AV100_FIXED_631M, "631m", NULL, 0, 631000000, },
71 { HI3559AV100_FIXED_600M, "600m", NULL, 0, 600000000, },
72 { HI3559AV100_FIXED_568M, "568m", NULL, 0, 568000000, },
73 { HI3559AV100_FIXED_500M, "500m", NULL, 0, 500000000, },
74 { HI3559AV100_FIXED_475M, "475m", NULL, 0, 475000000, },
75 { HI3559AV100_FIXED_428M, "428m", NULL, 0, 428000000, },
76 { HI3559AV100_FIXED_400M, "400m", NULL, 0, 400000000, },
77 { HI3559AV100_FIXED_396M, "396m", NULL, 0, 396000000, },
78 { HI3559AV100_FIXED_300M, "300m", NULL, 0, 300000000, },
79 { HI3559AV100_FIXED_250M, "250m", NULL, 0, 250000000, },
80 { HI3559AV100_FIXED_200M, "200m", NULL, 0, 200000000, },
81 { HI3559AV100_FIXED_198M, "198m", NULL, 0, 198000000, },
82 { HI3559AV100_FIXED_187p5M, "187p5m", NULL, 0, 187500000, },
83 { HI3559AV100_FIXED_150M, "150m", NULL, 0, 150000000, },
84 { HI3559AV100_FIXED_148p5M, "148p5m", NULL, 0, 1485000000, },
85 { HI3559AV100_FIXED_125M, "125m", NULL, 0, 125000000, },
86 { HI3559AV100_FIXED_107M, "107m", NULL, 0, 107000000, },
87 { HI3559AV100_FIXED_100M, "100m", NULL, 0, 100000000, },
88 { HI3559AV100_FIXED_99M, "99m", NULL, 0, 99000000, },
89 { HI3559AV100_FIXED_75M, "75m", NULL, 0, 75000000, },
90 { HI3559AV100_FIXED_74p25M, "74p25m", NULL, 0, 74250000, },
91 { HI3559AV100_FIXED_72M, "72m", NULL, 0, 72000000, },
92 { HI3559AV100_FIXED_60M, "60m", NULL, 0, 60000000, },
93 { HI3559AV100_FIXED_54M, "54m", NULL, 0, 54000000, },
94 { HI3559AV100_FIXED_50M, "50m", NULL, 0, 50000000, },
95 { HI3559AV100_FIXED_49p5M, "49p5m", NULL, 0, 49500000, },
96 { HI3559AV100_FIXED_37p125M, "37p125m", NULL, 0, 37125000, },
97 { HI3559AV100_FIXED_36M, "36m", NULL, 0, 36000000, },
98 { HI3559AV100_FIXED_32p4M, "32p4m", NULL, 0, 32400000, },
99 { HI3559AV100_FIXED_27M, "27m", NULL, 0, 27000000, },
100 { HI3559AV100_FIXED_25M, "25m", NULL, 0, 25000000, },
101 { HI3559AV100_FIXED_24M, "24m", NULL, 0, 24000000, },
102 { HI3559AV100_FIXED_12M, "12m", NULL, 0, 12000000, },
103 { HI3559AV100_FIXED_3M, "3m", NULL, 0, 3000000, },
104 { HI3559AV100_FIXED_1p6M, "1p6m", NULL, 0, 1600000, },
105 { HI3559AV100_FIXED_400K, "400k", NULL, 0, 400000, },
106 { HI3559AV100_FIXED_100K, "100k", NULL, 0, 100000, },
132 static const u32 fmc_mux_table[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
133 static const u32 mmc_mux_table[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
134 static const u32 sysapb_mux_table[] = { 0, 1 };
135 static const u32 sysbus_mux_table[] = { 0, 1 };
136 static const u32 uart_mux_table[] = { 0, 1, 2 };
137 static const u32 a73_clksel_mux_table[] = { 0, 1, 2 };
142 CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table,
146 CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table,
150 CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table,
155 CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table,
160 CLK_SET_RATE_PARENT, 0x23c, 24, 3, 0, mmc_mux_table,
165 CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table
170 CLK_SET_RATE_PARENT, 0xe8, 0, 1, 0, sysbus_mux_table
175 CLK_SET_RATE_PARENT, 0x198, 28, 2, 0, uart_mux_table
180 CLK_SET_RATE_PARENT, 0xe4, 0, 2, 0, a73_clksel_mux_table
187 CLK_SET_RATE_PARENT, 0x170, 1, 0,
191 CLK_SET_RATE_PARENT, 0x1a8, 28, 0,
195 CLK_SET_RATE_PARENT, 0x1ec, 28, 0,
199 CLK_SET_RATE_PARENT, 0x214, 28, 0,
203 CLK_SET_RATE_PARENT, 0x23c, 28, 0,
207 CLK_SET_RATE_PARENT, 0x198, 23, 0,
211 CLK_SET_RATE_PARENT, 0x198, 24, 0,
215 CLK_SET_RATE_PARENT, 0x198, 25, 0,
219 CLK_SET_RATE_PARENT, 0x198, 26, 0,
223 CLK_SET_RATE_PARENT, 0x198, 27, 0,
227 CLK_SET_RATE_PARENT, 0x0174, 1, 0,
231 CLK_SET_RATE_PARENT, 0x0174, 5, 0,
235 CLK_SET_RATE_PARENT, 0x0174, 3, 0,
239 CLK_SET_RATE_PARENT, 0x0174, 7, 0,
243 CLK_SET_RATE_PARENT, 0x01a0, 16, 0,
247 CLK_SET_RATE_PARENT, 0x01a0, 17, 0,
251 CLK_SET_RATE_PARENT, 0x01a0, 18, 0,
255 CLK_SET_RATE_PARENT, 0x01a0, 19, 0,
259 CLK_SET_RATE_PARENT, 0x01a0, 20, 0,
263 CLK_SET_RATE_PARENT, 0x01a0, 21, 0,
267 CLK_SET_RATE_PARENT, 0x01a0, 22, 0,
271 CLK_SET_RATE_PARENT, 0x01a0, 23, 0,
275 CLK_SET_RATE_PARENT, 0x01a0, 24, 0,
279 CLK_SET_RATE_PARENT, 0x01a0, 25, 0,
283 CLK_SET_RATE_PARENT, 0x01a0, 26, 0,
287 CLK_SET_RATE_PARENT, 0x01a0, 27, 0,
291 CLK_SET_RATE_PARENT, 0x0198, 16, 0,
295 CLK_SET_RATE_PARENT, 0x0198, 17, 0,
299 CLK_SET_RATE_PARENT, 0x0198, 18, 0,
303 CLK_SET_RATE_PARENT, 0x0198, 19, 0,
307 CLK_SET_RATE_PARENT, 0x0198, 20, 0,
311 CLK_SET_RATE_PARENT, 0x0198, 21, 0,
315 CLK_SET_RATE_PARENT, 0x0198, 22, 0,
319 CLK_SET_RATE_PARENT, 0x16c, 6, 0,
323 CLK_SET_RATE_PARENT, 0x16c, 5, 0,
327 CLK_SET_RATE_PARENT, 0x16c, 9, 0,
331 CLK_SET_RATE_PARENT, 0x16c, 8, 0,
335 CLK_SET_RATE_PARENT, 0x14c, 5, 0,
341 HI3559AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
342 0x4, 0, 12, 12, 6
345 HI3559AV100_GPLL_CLK, "gpll", NULL, 0x20, 0, 24, 24, 3, 28, 3,
346 0x24, 0, 12, 12, 6
362 *frac_val = 0; in hi3559av100_calc_pll()
380 postdiv1_val = postdiv2_val = 0; in clk_pll_set_rate()
403 return 0; in clk_pll_set_rate()
440 rate = 0; in clk_pll_recalc_rate()
467 for (i = 0; i < nums; i++) { in hisi_clk_register_pll()
469 init.flags = 0; in hisi_clk_register_pll()
472 init.num_parents = (clks[i].parent_name ? 1 : 0); in hisi_clk_register_pll()
569 { HI3559AV100_SHUB_SOURCE_SOC_24M, "clk_source_24M", NULL, 0, 24000000UL, },
570 { HI3559AV100_SHUB_SOURCE_SOC_200M, "clk_source_200M", NULL, 0, 200000000UL, },
571 { HI3559AV100_SHUB_SOURCE_SOC_300M, "clk_source_300M", NULL, 0, 300000000UL, },
572 { HI3559AV100_SHUB_SOURCE_PLL, "clk_source_PLL", NULL, 0, 192000000UL, },
573 { HI3559AV100_SHUB_I2C0_CLK, "clk_shub_i2c0", NULL, 0, 48000000UL, },
574 { HI3559AV100_SHUB_I2C1_CLK, "clk_shub_i2c1", NULL, 0, 48000000UL, },
575 { HI3559AV100_SHUB_I2C2_CLK, "clk_shub_i2c2", NULL, 0, 48000000UL, },
576 { HI3559AV100_SHUB_I2C3_CLK, "clk_shub_i2c3", NULL, 0, 48000000UL, },
577 { HI3559AV100_SHUB_I2C4_CLK, "clk_shub_i2c4", NULL, 0, 48000000UL, },
578 { HI3559AV100_SHUB_I2C5_CLK, "clk_shub_i2c5", NULL, 0, 48000000UL, },
579 { HI3559AV100_SHUB_I2C6_CLK, "clk_shub_i2c6", NULL, 0, 48000000UL, },
580 { HI3559AV100_SHUB_I2C7_CLK, "clk_shub_i2c7", NULL, 0, 48000000UL, },
581 { HI3559AV100_SHUB_UART_CLK_32K, "clk_uart_32K", NULL, 0, 32000UL, },
585 static u32 shub_source_clk_mux_table[] = {0, 1, 2, 3};
590 static u32 shub_uart_source_clk_mux_table[] = {0, 1, 2, 3};
599 0, 0x0, 0, 2, 0, shub_source_clk_mux_table,
605 0, 0x1c, 28, 2, 0, shub_uart_source_clk_mux_table,
611 static struct clk_div_table shub_spi_clk_table[] = {{0, 8}, {1, 4}, {2, 2}, {/*sentinel*/}};
615 { HI3559AV100_SHUB_SPI_SOURCE_CLK, "clk_spi_clk", "shub_clk", 0, 0x20, 24, 2,
618 { HI3559AV100_SHUB_UART_DIV_CLK, "clk_uart_div_clk", "shub_clk", 0, 0x1c, 28, 2,
627 0, 0x20, 1, 0,
631 0, 0x20, 5, 0,
635 0, 0x20, 9, 0,
640 0, 0x1c, 1, 0,
644 0, 0x1c, 5, 0,
648 0, 0x1c, 9, 0,
652 0, 0x1c, 13, 0,
656 0, 0x1c, 17, 0,
660 0, 0x1c, 21, 0,
664 0, 0x1c, 25, 0,
669 0, 0x24, 4, 0,
681 val = readl_relaxed(crg_base + 0x20); in hi3559av100_shub_default_clk_set()
682 val |= (0x2 << 24); in hi3559av100_shub_default_clk_set()
683 writel_relaxed(val, crg_base + 0x20); in hi3559av100_shub_default_clk_set()
686 val = readl_relaxed(crg_base + 0x1C); in hi3559av100_shub_default_clk_set()
687 val |= (0x1 << 28); in hi3559av100_shub_default_clk_set()
688 writel_relaxed(val, crg_base + 0x1C); in hi3559av100_shub_default_clk_set()
693 return 0; in hi3559av100_shub_default_clk_set()
807 return 0; in hi3559av100_crg_probe()