clk/davinci/pll.h

1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/clk-provider.h>
20 #define PLL_PREDIV_FIXED_DIV		BIT(3) /* fixed divider value */
23 #define PLL_POSTDIV_FIXED_DIV		BIT(6) /* fixed divider value */
28 /** davinci_pll_clk_info - controller-specific PLL info
35  * @pllout_min_rate: Minimum allowable rate for PLLOUT
36  * @pllout_max_rate: Maximum allowable rate for PLLOUT
51 #define SYSCLK_ARM_RATE		BIT(0) /* Controls ARM rate */
53 #define SYSCLK_FIXED_DIV	BIT(2) /* Fixed divider */
55 /** davinci_pll_sysclk_info - SYSCLKn-specific info
57  * @parent_name: The name of the parent clock
79 /** davinci_pll_obsclk_info - OBSCLK-specific info
81  * @parent_names: Array of names of the parent clocks
123 /* Platform-specific callbacks */