124 	/* div == 0 is actually the highest divisor */  in vt8500_dclk_recalc_rate()
135 	u32 divisor;  in vt8500_dclk_round_rate()  local
140 	divisor = *prate / rate;  in vt8500_dclk_round_rate()
142 	/* If prate / rate would be decimal, incr the divisor */  in vt8500_dclk_round_rate()
143 	if (rate * divisor < *prate)  in vt8500_dclk_round_rate()
144 		divisor++;  in vt8500_dclk_round_rate()
147 	 * If this is a request for SDMMC we have to adjust the divisor  in vt8500_dclk_round_rate()
150 	if ((cdev->div_mask == 0x3F) && (divisor > 31)) {  in vt8500_dclk_round_rate()
151 		divisor = 64 * ((divisor / 64) + 1);  in vt8500_dclk_round_rate()
154 	return *prate / divisor;  in vt8500_dclk_round_rate()
161 	u32 divisor;  in vt8500_dclk_set_rate()  local
167 	divisor =  parent_rate / rate;  in vt8500_dclk_set_rate()
169 	if (divisor == cdev->div_mask + 1)  in vt8500_dclk_set_rate()
170 		divisor = 0;  in vt8500_dclk_set_rate()
173 	if ((cdev->div_mask == 0x3F) && (divisor > 31)) {  in vt8500_dclk_set_rate()
175 		 * Bit 5 is a fixed /64 predivisor. If the requested divisor  in vt8500_dclk_set_rate()
176 		 * is >31 then correct for the fixed divisor being required.  in vt8500_dclk_set_rate()
178 		divisor = 0x20 + (divisor / 64);  in vt8500_dclk_set_rate()
181 	if (divisor > cdev->div_mask) {  in vt8500_dclk_set_rate()
182 		pr_err("%s: invalid divisor for clock\n", __func__);  in vt8500_dclk_set_rate()
189 	writel(divisor, cdev->div_reg);  in vt8500_dclk_set_rate()
255 	rc = of_property_read_u32(node, "divisor-reg", &div_reg);  in vtwm_device_clk_init()
264 		of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);  in vtwm_device_clk_init()
401 	 * Divisor P cannot be calculated. Test all divisors and find where M  in wm8650_find_pll_bits()
427 	/* calculate frequency (MHz) after pre-divisor */  in wm8750_get_filter()