drivers/clk/clk-vt8500.c

122 		div = 64 * (div & 0x1f);  in vt8500_dclk_recalc_rate()
151 		divisor = 64 * ((divisor / 64) + 1);  in vt8500_dclk_round_rate()
175 		 * Bit 5 is a fixed /64 predivisor. If the requested divisor  in vt8500_dclk_set_rate()
178 		divisor = 0x20 + (divisor / 64);  in vt8500_dclk_set_rate()
380  * Where O1 is 900MHz...3GHz;
381  * O2 is 600MHz >= (M * parent) / P >= 300MHz;
382  * M is 36...120 [25MHz parent]; D is 1 or 2 or 4 or 8.
384  * D = 8: 37,5MHz...75MHz
385  * D = 4: 75MHz...150MHz
386  * D = 2: 150MHz...300MHz
387  * D = 1: 300MHz...600MHz
427 	/* calculate frequency (MHz) after pre-divisor */  in wm8750_get_filter()
431 		pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n",  in wm8750_get_filter()