Lines Matching refs:div_frc
172 u32 div_frc; member
360 u32 div_int, div_frc, val; in vc3_pll_recalc_rate() local
370 div_frc = val << 8; in vc3_pll_recalc_rate()
372 div_frc |= val; in vc3_pll_recalc_rate()
374 (div_int * VC3_2_POW_16 + div_frc) / VC3_2_POW_16); in vc3_pll_recalc_rate()
387 u64 div_frc; in vc3_pll_round_rate() local
401 div_frc = rate % *parent_rate; in vc3_pll_round_rate()
402 div_frc *= BIT(16) - 1; in vc3_pll_round_rate()
404 vc3->div_frc = min_t(u64, div64_ul(div_frc, *parent_rate), U16_MAX); in vc3_pll_round_rate()
406 (vc3->div_int * VC3_2_POW_16 + vc3->div_frc) / VC3_2_POW_16); in vc3_pll_round_rate()
428 vc3->div_frc >> 8); in vc3_pll_set_rate()
430 vc3->div_frc & 0xff); in vc3_pll_set_rate()