1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/clk-provider.h>
26 #define TPS68470_CLK_NAME "tps68470-clk"
41  *  frequency range of 3 MHz to 27 MHz by a programmable
43  *  available at the HCLK_A or HCLK_B pins are in the range
48  * PLL_REF_CLK should be as close as possible to 100kHz
53  * BOOST should be as close as possible to 2Mhz
56  * BUCK should be as close as possible to 5.2Mhz
80 	if (regmap_read(clkdata->regmap, TPS68470_REG_PLLCTL, &val))  in tps68470_clk_is_prepared()
90 	regmap_write(clkdata->regmap, TPS68470_REG_CLKCFG1,  in tps68470_clk_prepare()
94 	regmap_update_bits(clkdata->regmap, TPS68470_REG_PLLCTL,  in tps68470_clk_prepare()
111 	regmap_update_bits(clkdata->regmap, TPS68470_REG_PLLCTL, TPS68470_PLL_EN_MASK, 0);  in tps68470_clk_unprepare()
113 	/* ... and then tri-state the clock outputs. */  in tps68470_clk_unprepare()
114 	regmap_write(clkdata->regmap, TPS68470_REG_CLKCFG1, 0);  in tps68470_clk_unprepare()
121 	return clkdata->rate;  in tps68470_clk_recalc_rate()
135 		diff = clk_freqs[i].freq - rate;  in tps68470_clk_cfg_lookup()
164 		return -EINVAL;  in tps68470_clk_set_rate()
166 	regmap_write(clkdata->regmap, TPS68470_REG_BOOSTDIV, clk_freqs[idx].boostdiv);  in tps68470_clk_set_rate()
167 	regmap_write(clkdata->regmap, TPS68470_REG_BUCKDIV, clk_freqs[idx].buckdiv);  in tps68470_clk_set_rate()
168 	regmap_write(clkdata->regmap, TPS68470_REG_PLLSWR, TPS68470_PLLSWR_DEFAULT);  in tps68470_clk_set_rate()
169 	regmap_write(clkdata->regmap, TPS68470_REG_XTALDIV, clk_freqs[idx].xtaldiv);  in tps68470_clk_set_rate()
170 	regmap_write(clkdata->regmap, TPS68470_REG_PLLDIV, clk_freqs[idx].plldiv);  in tps68470_clk_set_rate()
171 	regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV, clk_freqs[idx].postdiv);  in tps68470_clk_set_rate()
172 	regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV2, clk_freqs[idx].postdiv);  in tps68470_clk_set_rate()
173 	regmap_write(clkdata->regmap, TPS68470_REG_CLKCFG2, TPS68470_CLKCFG2_DRV_STR_2MA);  in tps68470_clk_set_rate()
175 	regmap_write(clkdata->regmap, TPS68470_REG_PLLCTL,  in tps68470_clk_set_rate()
179 	clkdata->rate = rate;  in tps68470_clk_set_rate()
195 	struct tps68470_clk_platform_data *pdata = pdev->dev.platform_data;  in tps68470_clk_probe()
207 	tps68470_clkdata = devm_kzalloc(&pdev->dev, sizeof(*tps68470_clkdata),  in tps68470_clk_probe()
210 		return -ENOMEM;  in tps68470_clk_probe()
212 	tps68470_clkdata->regmap = dev_get_drvdata(pdev->dev.parent);  in tps68470_clk_probe()
213 	tps68470_clkdata->clkout_hw.init = &tps68470_clk_initdata;  in tps68470_clk_probe()
216 	tps68470_clk_set_rate(&tps68470_clkdata->clkout_hw, clk_freqs[0].freq, 0);  in tps68470_clk_probe()
218 	ret = devm_clk_hw_register(&pdev->dev, &tps68470_clkdata->clkout_hw);  in tps68470_clk_probe()
222 	ret = devm_clk_hw_register_clkdev(&pdev->dev, &tps68470_clkdata->clkout_hw,  in tps68470_clk_probe()
228 		for (i = 0; i < pdata->n_consumers; i++) {  in tps68470_clk_probe()
229 			consumer = &pdata->consumers[i];  in tps68470_clk_probe()
230 			ret = devm_clk_hw_register_clkdev(&pdev->dev,  in tps68470_clk_probe()
231 							  &tps68470_clkdata->clkout_hw,  in tps68470_clk_probe()
232 							  consumer->consumer_con_id,  in tps68470_clk_probe()
233 							  consumer->consumer_dev_name);  in tps68470_clk_probe()
248  * The ACPI tps68470 probe-ordering depends on the clk/gpio/regulator drivers
249  * registering before the drivers for the camera-sensors which use them bind.
264 MODULE_ALIAS("platform:tps68470-clk");