Lines Matching refs:STM32F4_RCC_DCKCFGR
39 #define STM32F4_RCC_DCKCFGR 0x8c macro
557 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},
560 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },
563 STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table },
1189 STM32F4_RCC_DCKCFGR, 20, 3,
1195 STM32F4_RCC_DCKCFGR, 22, 3,
1216 STM32F4_RCC_DCKCFGR, 20, 3,
1222 STM32F4_RCC_DCKCFGR, 22, 3,
1228 STM32F4_RCC_DCKCFGR, 27, 1,
1234 STM32F4_RCC_DCKCFGR, 28, 1,
1240 STM32F4_RCC_DCKCFGR, 29, 1,
1261 STM32F4_RCC_DCKCFGR, 20, 3,
1267 STM32F4_RCC_DCKCFGR, 22, 3,
1407 STM32F4_RCC_DCKCFGR, 20, 3,
1413 STM32F4_RCC_DCKCFGR, 22, 3,
1550 STM32F4_RCC_DCKCFGR, 25, 1,
1557 STM32F4_RCC_DCKCFGR, 26, 1,