1 // SPDX-License-Identifier: GPL-2.0-only
5  * Inspired by clk-asm9260.c .
8 #include <linux/clk-provider.h>
25 #include <dt-bindings/clock/stm32fx-clock.h>
42 #define NONE -1
48 	u8	offset;  member
403  * The APBx dividers are power-of-two dividers and, if *not* running in 1:1
420 	if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))  in clk_apb_mul_recalc_rate()
432 	if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))  in clk_apb_mul_round_rate()
472 		return ERR_PTR(-ENOMEM);  in clk_register_apb_mul()
474 	am->bit_idx = bit_idx;  in clk_register_apb_mul()
475 	am->hw.init = &init;  in clk_register_apb_mul()
483 	clk = clk_register(dev, &am->hw);  in clk_register_apb_mul()
515 	u8 offset;  member
529 	u8 offset;  member
538 	u8 offset;  member
544 	{ "vco",     STM32F4_RCC_PLLCFGR,    24, 25 },
545 	{ "vco-i2s", STM32F4_RCC_PLLI2SCFGR, 26, 27 },
546 	{ "vco-sai", STM32F4_RCC_PLLSAICFGR, 28, 29 },
556 	{ CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q",
559 	{ CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q",
562 	{ NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
588 	{ PLL_I2S, 192, { NULL,  "plli2s-q", "plli2s-r" } },
589 	{ PLL_SAI,  49, { NULL,  "pllsai-q", "pllsai-r" } },
593 	{ PLL,	   50, { "pll",	     "pll-q",    "pll-r"    } },
594 	{ PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
595 	{ PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
618 		bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx));  in stm32f4_pll_enable()
620 	} while (bit_status && --timeout);  in stm32f4_pll_enable()
637 	n = (readl(base + pll->offset) >> 6) & 0x1ff;  in stm32f4_pll_recalc()
651 	if (n < pll->n_start)  in stm32f4_pll_round_rate()
652 		n = pll->n_start;  in stm32f4_pll_round_rate()
676 	val = readl(base + pll->offset) & ~(0x1ff << 6);  in stm32f4_pll_set_rate()
678 	writel(val | ((n & 0x1ff) <<  6), base + pll->offset);  in stm32f4_pll_set_rate()
722 	pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll);  in stm32f4_pll_div_set_rate()
725 		stm32f4_pll_disable(pll_div->hw_pll);  in stm32f4_pll_div_set_rate()
730 		stm32f4_pll_enable(pll_div->hw_pll);  in stm32f4_pll_div_set_rate()
755 		return ERR_PTR(-ENOMEM);  in clk_register_pll_div()
764 	pll_div->div.reg = reg;  in clk_register_pll_div()
765 	pll_div->div.shift = shift;  in clk_register_pll_div()
766 	pll_div->div.width = width;  in clk_register_pll_div()
767 	pll_div->div.flags = clk_divider_flags;  in clk_register_pll_div()
768 	pll_div->div.lock = lock;  in clk_register_pll_div()
769 	pll_div->div.table = table;  in clk_register_pll_div()
770 	pll_div->div.hw.init = &init;  in clk_register_pll_div()
772 	pll_div->hw_pll = pll_hw;  in clk_register_pll_div()
775 	hw = &pll_div->div.hw;  in clk_register_pll_div()
794 	const struct stm32f4_vco_data *vco;  in stm32f4_rcc_register_pll()  local
799 		return ERR_PTR(-ENOMEM);  in stm32f4_rcc_register_pll()
801 	vco = &vco_data[data->pll_num];  in stm32f4_rcc_register_pll()
803 	init.name = vco->vco_name;  in stm32f4_rcc_register_pll()
809 	pll->gate.lock = lock;  in stm32f4_rcc_register_pll()
810 	pll->gate.reg = base + STM32F4_RCC_CR;  in stm32f4_rcc_register_pll()
811 	pll->gate.bit_idx = vco->bit_idx;  in stm32f4_rcc_register_pll()
812 	pll->gate.hw.init = &init;  in stm32f4_rcc_register_pll()
814 	pll->offset = vco->offset;  in stm32f4_rcc_register_pll()
815 	pll->n_start = data->n_start;  in stm32f4_rcc_register_pll()
816 	pll->bit_rdy_idx = vco->bit_rdy_idx;  in stm32f4_rcc_register_pll()
817 	pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1;  in stm32f4_rcc_register_pll()
819 	reg = base + pll->offset;  in stm32f4_rcc_register_pll()
821 	pll_hw = &pll->gate.hw;  in stm32f4_rcc_register_pll()
829 		if (data->div_name[i])  in stm32f4_rcc_register_pll()
830 			clk_register_pll_div(data->div_name[i],  in stm32f4_rcc_register_pll()
831 					vco->vco_name,  in stm32f4_rcc_register_pll()
845  * offset into our struct clock array.
853 			return -EINVAL;  in stm32f4_rcc_lookup_clk_idx()
863 		return -EINVAL;  in stm32f4_rcc_lookup_clk_idx()
869 	return stm32fx_end_primary_clk - 1 + hweight64(table[0]) +  in stm32f4_rcc_lookup_clk_idx()
877 	int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]);  in stm32f4_rcc_lookup_clk()
880 		return ERR_PTR(-EINVAL);  in stm32f4_rcc_lookup_clk()
930 		bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy_idx));  in rgclk_enable()
934 	} while (bit_status && --timeout);  in rgclk_enable()
969 		return ERR_PTR(-ENOMEM);  in clk_register_rgate()
977 	rgate->bit_rdy_idx = bit_rdy_idx;  in clk_register_rgate()
979 	rgate->gate.lock = lock;  in clk_register_rgate()
980 	rgate->gate.reg = reg;  in clk_register_rgate()
981 	rgate->gate.bit_idx = bit_idx;  in clk_register_rgate()
982 	rgate->gate.hw.init = &init;  in clk_register_rgate()
984 	hw = &rgate->gate.hw;  in clk_register_rgate()
1064 		hw = ERR_PTR(-EINVAL);  in stm32_register_cclk()
1071 		hw = ERR_PTR(-EINVAL);  in stm32_register_cclk()
1075 	gate->reg = reg;  in stm32_register_cclk()
1076 	gate->bit_idx = bit_idx;  in stm32_register_cclk()
1077 	gate->flags = 0;  in stm32_register_cclk()
1078 	gate->lock = lock;  in stm32_register_cclk()
1080 	mux->reg = reg;  in stm32_register_cclk()
1081 	mux->shift = shift;  in stm32_register_cclk()
1082 	mux->mask = 3;  in stm32_register_cclk()
1083 	mux->flags = 0;  in stm32_register_cclk()
1086 			&mux->hw, &cclk_mux_ops,  in stm32_register_cclk()
1088 			&gate->hw, &cclk_gate_ops,  in stm32_register_cclk()
1117 	"no-clock", "lse", "lsi", "hse-rtc"
1120 static const char *pll_src = "pll-src";
1124 static const char *dsi_parent[2] = { NULL, "pll-r" };
1126 static const char *lcd_parent[1] = { "pllsai-r-div" };
1128 static const char *i2s_parents[2] = { "plli2s-r", NULL };
1130 static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL,
1131 	"no-clock" };
1133 static const char *pll48_parents[2] = { "pll-q", "pllsai-p" };
1139 static const char *spdif_parent[1] = { "plli2s-p" };
1146 static const char *i2c_parents[4] = { "apb1_div", "sys", "hsi", "no-clock" };
1176 		CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1188 		CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1194 		CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1203 		CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1215 		CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1221 		CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1248 		CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1284 		CLK_HDMI_CEC, "hdmi-cec",
1291 		CLK_SPDIF, "spdif-rx",
1394 		CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1436 		CLK_HDMI_CEC, "hdmi-cec",
1443 		CLK_SPDIF, "spdif-rx",
1605 		.compatible = "st,stm32f42xx-rcc",
1609 		.compatible = "st,stm32f469-rcc",
1613 		.compatible = "st,stm32f746-rcc",
1617 		.compatible = "st,stm32f769-rcc",
1638 			hw = ERR_PTR(-EINVAL);  in stm32_register_aux_clk()
1642 		gate->reg = base + offset_gate;  in stm32_register_aux_clk()
1643 		gate->bit_idx = bit_idx;  in stm32_register_aux_clk()
1644 		gate->flags = 0;  in stm32_register_aux_clk()
1645 		gate->lock = lock;  in stm32_register_aux_clk()
1646 		gate_hw = &gate->hw;  in stm32_register_aux_clk()
1653 			hw = ERR_PTR(-EINVAL);  in stm32_register_aux_clk()
1657 		mux->reg = base + offset_mux;  in stm32_register_aux_clk()
1658 		mux->shift = shift;  in stm32_register_aux_clk()
1659 		mux->mask = mask;  in stm32_register_aux_clk()
1660 		mux->flags = 0;  in stm32_register_aux_clk()
1661 		mux_hw = &mux->hw;  in stm32_register_aux_clk()
1666 		hw = ERR_PTR(-EINVAL);  in stm32_register_aux_clk()
1710 	data = match->data;  in stm32f4_rcc_init()
1712 	stm32fx_end_primary_clk = data->end_primary;  in stm32f4_rcc_init()
1714 	clks = kmalloc_array(data->gates_num + stm32fx_end_primary_clk,  in stm32f4_rcc_init()
1719 	stm32f4_gate_map = data->gates_map;  in stm32f4_rcc_init()
1730 	if (of_device_is_compatible(np, "st,stm32f769-rcc")) {  in stm32f4_rcc_init()
1751 	stm32f4_rcc_register_pll("vco_in", &data->pll_data[0],  in stm32f4_rcc_init()
1755 			&data->pll_data[1], &stm32f4_clk_lock);  in stm32f4_rcc_init()
1758 			&data->pll_data[2], &stm32f4_clk_lock);  in stm32f4_rcc_init()
1766 		hw = clk_register_pll_div(post_div->name,  in stm32f4_rcc_init()
1767 				post_div->parent,  in stm32f4_rcc_init()
1768 				post_div->flag,  in stm32f4_rcc_init()
1769 				base + post_div->offset,  in stm32f4_rcc_init()
1770 				post_div->shift,  in stm32f4_rcc_init()
1771 				post_div->width,  in stm32f4_rcc_init()
1772 				post_div->flag_div,  in stm32f4_rcc_init()
1773 				post_div->div_table,  in stm32f4_rcc_init()
1774 				clks[post_div->pll_idx],  in stm32f4_rcc_init()
1777 		if (post_div->idx != NO_IDX)  in stm32f4_rcc_init()
1778 			clks[post_div->idx] = hw;  in stm32f4_rcc_init()
1808 	for (n = 0; n < data->gates_num; n++) {  in stm32f4_rcc_init()
1813 		gd = &data->gates_data[n];  in stm32f4_rcc_init()
1814 		secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) +  in stm32f4_rcc_init()
1815 			gd->bit_idx;  in stm32f4_rcc_init()
1822 		    NULL, gd->name, gd->parent_name, gd->flags,  in stm32f4_rcc_init()
1823 		    base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock);  in stm32f4_rcc_init()
1827 			       np, gd->name);  in stm32f4_rcc_init()
1832 	clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0,  in stm32f4_rcc_init()
1840 	clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0,  in stm32f4_rcc_init()
1848 	clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse",  in stm32f4_rcc_init()
1853 		pr_err("Unable to register hse-rtc clock\n");  in stm32f4_rcc_init()
1865 	for (n = 0; n < data->aux_clk_num; n++) {  in stm32f4_rcc_init()
1869 		aux_clk = &data->aux_clk[n];  in stm32f4_rcc_init()
1871 		hw = stm32_register_aux_clk(aux_clk->name,  in stm32f4_rcc_init()
1872 				aux_clk->parent_names, aux_clk->num_parents,  in stm32f4_rcc_init()
1873 				aux_clk->offset_mux, aux_clk->shift,  in stm32f4_rcc_init()
1874 				aux_clk->mask, aux_clk->offset_gate,  in stm32f4_rcc_init()
1875 				aux_clk->bit_idx, aux_clk->flags,  in stm32f4_rcc_init()
1879 			pr_warn("Unable to register %s clk\n", aux_clk->name);  in stm32f4_rcc_init()
1883 		if (aux_clk->idx != NO_IDX)  in stm32f4_rcc_init()
1884 			clks[aux_clk->idx] = hw;  in stm32f4_rcc_init()
1887 	if (of_device_is_compatible(np, "st,stm32f746-rcc")) {  in stm32f4_rcc_init()
1902 CLK_OF_DECLARE_DRIVER(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
1903 CLK_OF_DECLARE_DRIVER(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);
1904 CLK_OF_DECLARE_DRIVER(stm32f746_rcc, "st,stm32f746-rcc", stm32f4_rcc_init);
1905 CLK_OF_DECLARE_DRIVER(stm32f769_rcc, "st,stm32f769-rcc", stm32f4_rcc_init);