1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Microchip Sparx5 SoC Clock driver.
12 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/microchip,sparx5.h>
61 	unsigned long rate = parent_rate / conf->div;  in s5_calc_freq()
63 	if (conf->rot_ena) {  in s5_calc_freq()
64 		int sign = conf->rot_dir ? -1 : 1;  in s5_calc_freq()
65 		int divt = sel_rates[conf->rot_sel] * (1 + conf->pre_div);  in s5_calc_freq()
85 	conf->div = div;  in s5_search_fractional()
86 	conf->rot_ena = 1;	/* Fractional rate */  in s5_search_fractional()
89 		conf->rot_dir = !!d;  in s5_search_fractional()
91 			conf->pre_div = i;  in s5_search_fractional()
93 				conf->rot_sel = j;  in s5_search_fractional()
94 				conf->freq = s5_calc_freq(parent_rate, conf);  in s5_search_fractional()
95 				cur_offset = abs(rate - conf->freq);  in s5_search_fractional()
129 				if (abs(rate - alt1.freq) <  in s5_calc_params()
130 				    abs(rate - alt2.freq))  in s5_calc_params()
139 		conf->div = parent_rate / rate;  in s5_calc_params()
142 	return conf->freq;  in s5_calc_params()
148 	u32 val = readl(pll->reg);  in s5_pll_enable()
151 	writel(val, pll->reg);  in s5_pll_enable()
159 	u32 val = readl(pll->reg);  in s5_pll_disable()
162 	writel(val, pll->reg);  in s5_pll_disable()
176 		return -EOPNOTSUPP;  in s5_pll_set_rate()
178 	val = readl(pll->reg) & PLL_CLK_ENA;  in s5_pll_set_rate()
187 	writel(val, pll->reg);  in s5_pll_set_rate()
199 	val = readl(pll->reg);  in s5_pll_recalc_rate()
235 	unsigned int idx = clkspec->args[0];  in s5_clk_hw_get()
239 		return ERR_PTR(-EINVAL);  in s5_clk_hw_get()
242 	return &s5_clk->s5_hw[idx].hw;  in s5_clk_hw_get()
247 	struct device *dev = &pdev->dev;  in s5_clk_probe()
259 		return -ENOMEM;  in s5_clk_probe()
261 	s5_clk->base = devm_platform_ioremap_resource(pdev, 0);  in s5_clk_probe()
262 	if (IS_ERR(s5_clk->base))  in s5_clk_probe()
263 		return PTR_ERR(s5_clk->base);  in s5_clk_probe()
266 		struct s5_hw_clk *s5_hw = &s5_clk->s5_hw[i];  in s5_clk_probe()
269 		s5_hw->reg = s5_clk->base + (i * 4);  in s5_clk_probe()
270 		s5_hw->hw.init = &init;  in s5_clk_probe()
271 		ret = devm_clk_hw_register(dev, &s5_hw->hw);  in s5_clk_probe()
283 	{ .compatible = "microchip,sparx5-dpll", },
291 		.name = "sparx5-clk",