drivers/clk/clk-npcm7xx.c

1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
35 #define PLLCON_OTDV1	GENMASK(10, 8)
51 	val = readl_relaxed(pll->pllcon);  in npcm7xx_clk_pll_recalc_rate()
79 		return ERR_PTR(-ENOMEM);  in npcm7xx_clk_register_pll()
89 	pll->pllcon = pllcon;  in npcm7xx_clk_register_pll()
90 	pll->hw.init = &init;  in npcm7xx_clk_register_pll()
92 	hw = &pll->hw;  in npcm7xx_clk_register_pll()
142 	 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
143 	 * this specific clock.  Otherwise, set to -1.
159 	 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
160 	 * this specific clock.  Otherwise, set to -1.
172 	 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
173 	 * this specific clock.  Otherwise, set to -1.
197 #define NPCM7XX_CLK_S_AXI         "axi"  /*AKA CLK2*/
222 #define NPCM7XX_CLK_S_ADC         "adc"
286 	{NPCM7XX_PLLCON0, NPCM7XX_CLK_S_PLL0, NPCM7XX_CLK_S_REFCLK, 0, -1},
289 	NPCM7XX_CLK_S_REFCLK, 0, -1},
292 	NPCM7XX_CLK_S_REFCLK, 0, -1},
295 	NPCM7XX_CLK_S_REFCLK, 0, -1},
308 	pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
311 	pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
313 	{10, GENMASK(1, 0), sucksel_mux_table, NPCM7XX_CLK_S_SU_MUX,
314 	sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1},
317 	mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1},
320 	pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
323 	pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1},
326 	clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1},
329 	gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1},
332 	dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1},
339 	/*30-28 ADCCKDIV*/
342 	/*27-26 CLK4DIV*/
345 	/*25-21 TIMCKDIV*/
348 	/*20-16 UARTDIV*/
351 	/*15-11 MMCCKDIV*/
354 	/*10-6 AHB3CKDIV*/
357 	/*5-2 PCICKDIV*/
364 	/*31-30 APB4CKDIV*/
367 	/*29-28 APB3CKDIV*/
370 	/*27-26 APB2CKDIV*/
373 	/*25-24 APB1CKDIV*/
376 	/*23-22 APB5CKDIV*/
379 	/*20-16 CLKOUTDIV*/
382 	/*15-13 GFXCKDIV*/
385 	/*12-8 SUCKDIV*/
388 	/*7-4 SU48CKDIV*/
391 	,/*3-0 SD1CKDIV*/
395 	/*10-6 SPI0CKDV*/
398 	/*5-1 SPIXCKDV*/
429 	npcm7xx_clk_data->num = NPCM7XX_NUM_CLOCKS;  in npcm7xx_clk_init()
432 		npcm7xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);  in npcm7xx_clk_init()
438 		hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg,  in npcm7xx_clk_init()
439 			pll_data->name, pll_data->parent_name, pll_data->flags);  in npcm7xx_clk_init()
445 		if (pll_data->onecell_idx >= 0)  in npcm7xx_clk_init()
446 			npcm7xx_clk_data->hws[pll_data->onecell_idx] = hw;  in npcm7xx_clk_init()
469 			mux_data->name,  in npcm7xx_clk_init()
470 			mux_data->parent_names, mux_data->num_parents,  in npcm7xx_clk_init()
471 			mux_data->flags, clk_base + NPCM7XX_CLKSEL,  in npcm7xx_clk_init()
472 			mux_data->shift, mux_data->mask, 0,  in npcm7xx_clk_init()
473 			mux_data->table, &npcm7xx_clk_lock);  in npcm7xx_clk_init()
480 		if (mux_data->onecell_idx >= 0)  in npcm7xx_clk_init()
481 			npcm7xx_clk_data->hws[mux_data->onecell_idx] = hw;  in npcm7xx_clk_init()
488 		hw = clk_hw_register_divider(NULL, div_data->name,  in npcm7xx_clk_init()
489 				div_data->parent_name,  in npcm7xx_clk_init()
490 				div_data->flags,  in npcm7xx_clk_init()
491 				clk_base + div_data->reg,  in npcm7xx_clk_init()
492 				div_data->shift, div_data->width,  in npcm7xx_clk_init()
493 				div_data->clk_divider_flags, &npcm7xx_clk_lock);  in npcm7xx_clk_init()
499 		if (div_data->onecell_idx >= 0)  in npcm7xx_clk_init()
500 			npcm7xx_clk_data->hws[div_data->onecell_idx] = hw;  in npcm7xx_clk_init()
519 CLK_OF_DECLARE(npcm7xx_clk_init, "nuvoton,npcm750-clk", npcm7xx_clk_init);