Lines Matching +full:reg +full:- +full:init
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
10 #include <linux/clk-provider.h>
21 * prepare - clk_prepare only ensures that parents are prepared
22 * enable - clk_enable only ensures that parents are enabled
23 * rate - rate is only affected by parent switching. No clk_set_rate support
24 * parent - parent is adjustable through clk_set_parent
29 if (mux->flags & CLK_MUX_BIG_ENDIAN) in clk_mux_readl()
30 return ioread32be(mux->reg); in clk_mux_readl()
32 return readl(mux->reg); in clk_mux_readl()
37 if (mux->flags & CLK_MUX_BIG_ENDIAN) in clk_mux_writel()
38 iowrite32be(val, mux->reg); in clk_mux_writel()
40 writel(val, mux->reg); in clk_mux_writel()
54 return -EINVAL; in clk_mux_val_to_index()
58 val = ffs(val) - 1; in clk_mux_val_to_index()
61 val--; in clk_mux_val_to_index()
64 return -EINVAL; in clk_mux_val_to_index()
93 val = clk_mux_readl(mux) >> mux->shift; in clk_mux_get_parent()
94 val &= mux->mask; in clk_mux_get_parent()
96 return clk_mux_val_to_index(hw, mux->table, mux->flags, val); in clk_mux_get_parent()
102 u32 val = clk_mux_index_to_val(mux->table, mux->flags, index); in clk_mux_set_parent()
104 u32 reg; in clk_mux_set_parent() local
106 if (mux->lock) in clk_mux_set_parent()
107 spin_lock_irqsave(mux->lock, flags); in clk_mux_set_parent()
109 __acquire(mux->lock); in clk_mux_set_parent()
111 if (mux->flags & CLK_MUX_HIWORD_MASK) { in clk_mux_set_parent()
112 reg = mux->mask << (mux->shift + 16); in clk_mux_set_parent()
114 reg = clk_mux_readl(mux); in clk_mux_set_parent()
115 reg &= ~(mux->mask << mux->shift); in clk_mux_set_parent()
117 val = val << mux->shift; in clk_mux_set_parent()
118 reg |= val; in clk_mux_set_parent()
119 clk_mux_writel(mux, reg); in clk_mux_set_parent()
121 if (mux->lock) in clk_mux_set_parent()
122 spin_unlock_irqrestore(mux->lock, flags); in clk_mux_set_parent()
124 __release(mux->lock); in clk_mux_set_parent()
134 return clk_mux_determine_rate_flags(hw, req, mux->flags); in clk_mux_determine_rate()
154 unsigned long flags, void __iomem *reg, u8 shift, u32 mask, in __clk_hw_register_mux() argument
159 struct clk_init_data init = {}; in __clk_hw_register_mux() local
160 int ret = -EINVAL; in __clk_hw_register_mux()
163 u8 width = fls(mask) - ffs(mask) + 1; in __clk_hw_register_mux()
167 return ERR_PTR(-EINVAL); in __clk_hw_register_mux()
174 return ERR_PTR(-ENOMEM); in __clk_hw_register_mux()
176 init.name = name; in __clk_hw_register_mux()
178 init.ops = &clk_mux_ro_ops; in __clk_hw_register_mux()
180 init.ops = &clk_mux_ops; in __clk_hw_register_mux()
181 init.flags = flags; in __clk_hw_register_mux()
182 init.parent_names = parent_names; in __clk_hw_register_mux()
183 init.parent_data = parent_data; in __clk_hw_register_mux()
184 init.parent_hws = parent_hws; in __clk_hw_register_mux()
185 init.num_parents = num_parents; in __clk_hw_register_mux()
188 mux->reg = reg; in __clk_hw_register_mux()
189 mux->shift = shift; in __clk_hw_register_mux()
190 mux->mask = mask; in __clk_hw_register_mux()
191 mux->flags = clk_mux_flags; in __clk_hw_register_mux()
192 mux->lock = lock; in __clk_hw_register_mux()
193 mux->table = table; in __clk_hw_register_mux()
194 mux->hw.init = &init; in __clk_hw_register_mux()
196 hw = &mux->hw; in __clk_hw_register_mux()
220 unsigned long flags, void __iomem *reg, u8 shift, u32 mask, in __devm_clk_hw_register_mux() argument
227 return ERR_PTR(-ENOMEM); in __devm_clk_hw_register_mux()
230 parent_data, flags, reg, shift, mask, in __devm_clk_hw_register_mux()
246 unsigned long flags, void __iomem *reg, u8 shift, u32 mask, in clk_register_mux_table() argument
252 num_parents, flags, reg, shift, mask, in clk_register_mux_table()
256 return hw->clk; in clk_register_mux_table()