34 /* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */
75 /* 0x138 - 0x145 SYSREF, SYNC, and Device Config */
226 	bool sysref;  member
237  * @sysref_mux: select SYSREF source
238  * @sysref_pulse_cnt: number of SYSREF pulses generated while not in continuous
240  * @sysref_ddly: SYSREF digital delay value
243  * @sclk: reference to the internal sysref clock (SCLK)
721  *   (8.3.3.1 How to enable SYSREF)
774 	 *    transaction. If SYSREF local digital delay is not used, this step  in lmk04832_sclk_sync_sequence()
793 	 *    does not shift into continuous SYSREF mode.  in lmk04832_sclk_sync_sequence()
828 	 * 9. (optional) if SCLKx_y_DIS_MODE was used to mute SYSREF outputs  in lmk04832_sclk_sync_sequence()
902 		dev_err(lmk->dev, "SYSREF divider out of range\n");  in lmk04832_sclk_round_rate()
922 		dev_err(lmk->dev, "SYSREF divider out of range\n");  in lmk04832_sclk_set_rate()
1346 				      lmk->clkout[num].sysref));  in lmk04832_register_clkout()
1442 	device_property_read_u32(lmk->dev, "ti,sysref-ddly", &lmk->sysref_ddly);  in lmk04832_probe()
1445 	device_property_read_u32(lmk->dev, "ti,sysref-mux",  in lmk04832_probe()
1453 	device_property_read_u32(lmk->dev, "ti,sysref-pulse-count",  in lmk04832_probe()
1475 		lmk->clkout[reg].sysref =  in lmk04832_probe()
1476 			of_property_read_bool(child, "ti,clkout-sysref");  in lmk04832_probe()
1523 		dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n");  in lmk04832_probe()